mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
memory: Introduce $meminit_v2 cell, with EN input.
This commit is contained in:
parent
37d76deef1
commit
19720b970d
10 changed files with 86 additions and 13 deletions
|
@ -117,7 +117,7 @@ void rmunused_module_cells(Module *module, bool verbose)
|
|||
}
|
||||
|
||||
for (Cell *cell : module->cells()) {
|
||||
if (cell->type.in(ID($memwr), ID($meminit))) {
|
||||
if (cell->type.in(ID($memwr), ID($meminit), ID($meminit_v2))) {
|
||||
IdString mem_id = cell->getParam(ID::MEMID).decode_string();
|
||||
mem2cells[mem_id].insert(cell);
|
||||
}
|
||||
|
|
|
@ -558,7 +558,7 @@ struct WreducePass : public Pass {
|
|||
}
|
||||
}
|
||||
|
||||
if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
|
||||
if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit), ID($meminit_v2))) {
|
||||
IdString memid = c->getParam(ID::MEMID).decode_string();
|
||||
RTLIL::Memory *mem = module->memories.at(memid);
|
||||
if (mem->start_offset >= 0) {
|
||||
|
|
|
@ -559,6 +559,7 @@ struct SimInstance
|
|||
MemInit minit;
|
||||
minit.addr = mem.mem->start_offset;
|
||||
minit.data = mem.data;
|
||||
minit.en = Const(State::S1, mem.mem->width);
|
||||
mem.mem->inits.push_back(minit);
|
||||
mem.mem->emit();
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue