mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

memory: Introduce $meminit_v2 cell, with EN input.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-05-21 02:26:52 +02:00
parent 37d76deef1
commit 19720b970d
10 changed files with 86 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

12
kernel/rtlil.cc
View file

@ -1414,6 +1414,16 @@ namespace {
return;
}
if (cell->type == ID($meminit_v2)) {
param(ID::MEMID);
param(ID::PRIORITY);
port(ID::ADDR, param(ID::ABITS));
port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
port(ID::EN, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($mem)) {
param(ID::MEMID);
param(ID::SIZE);
@ -3177,7 +3187,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
bool RTLIL::Cell::has_memid() const
{
return type.in(ID($memwr), ID($memrd), ID($meminit));
return type.in(ID($memwr), ID($memrd), ID($meminit), ID($meminit_v2));
}
bool RTLIL::Cell::is_mem_cell() const