mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-14 18:06:16 +00:00
Code Activity

Add new lines

Browse source
This commit is contained in:
Akash Levy 2024-10-23 23:52:55 -07:00
parent 17c8567b02
commit 1953a42f0d
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
backends/verilog/verilog_backend.cc
View file

@ -367,9 +367,12 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
dump_sigchunk(f, sig.as_chunk()); dump_sigchunk(f, sig.as_chunk());
} else { } else {
f << stringf("{ "); f << stringf("{ ");
int i = 0;
for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) { for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
if (it != sig.chunks().rbegin()) if (it != sig.chunks().rbegin())
f << stringf(", "); f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
dump_sigchunk(f, *it, true); dump_sigchunk(f, *it, true);
} }
f << stringf(" }"); f << stringf(" }");