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Bump yosys and abc to latest

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This commit is contained in:
Akash Levy 2025-12-25 03:46:16 -05:00
commit 1941e8f042
24 changed files with 139 additions and 126 deletions
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2
passes/cmds/example_dt.cc
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@ -77,7 +77,7 @@ struct ExampleDtPass : public Pass
auto enqueue = [&](DriveSpec const &spec) {
int index = queue(spec);
if (index == GetSize(graph_nodes))
graph_nodes.emplace_back(compute_graph.add(ID($pending).id_string(), index).index());
graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index());
//if (index >= GetSize(graph_nodes))
return compute_graph[graph_nodes[index]];
};

1
passes/cmds/icell_liberty.cc
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@ -163,7 +163,6 @@ struct IcellLiberty : Pass {
log_header(d, "Executing ICELL_LIBERTY pass.\n");
size_t argidx;
IdString naming_attr;
std::string liberty_filename;
auto liberty_file = std::make_unique<std::ofstream>();

2
passes/cmds/printattrs.cc
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@ -45,7 +45,7 @@ struct PrintAttrsPass : public Pass {
return stringf("%*s", indent, "");
}
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)

2
passes/cmds/trace.cc
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@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor
log("#TRACE# Module delete: %s\n", log_id(module));
}
void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
}

5
passes/opt/opt_merge.cc
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@ -227,6 +227,11 @@ struct OptMergeWorker
ct.cell_types.erase(ID($anyconst));
ct.cell_types.erase(ID($allseq));
ct.cell_types.erase(ID($allconst));
ct.cell_types.erase(ID($check));
ct.cell_types.erase(ID($assert));
ct.cell_types.erase(ID($assume));
ct.cell_types.erase(ID($live));
ct.cell_types.erase(ID($cover));
log("Finding identical cells in module `%s'.\n", module->name);
assign_map.set(module);

2
passes/techmap/abc.cc
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@ -256,7 +256,7 @@ std::optional<AbcProcess> spawn_abc(const char* abc_exe, DeferredLogs &logs) {
char arg1[] = "-s";
char* argv[] = { strdup(abc_exe), arg1, nullptr };
if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) {
logs.log_error("posix_spawnp %s failed", abc_exe);
logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerrorname_np(errno));
return std::nullopt;
}
free(argv[0]);

2
passes/techmap/bufnorm.cc
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@ -415,7 +415,7 @@ struct BufnormPass : public Pass {
return mapped_bits.at(bit);
};
auto make_buffer_f = [&](const IdString &type, const SigSpec &src, const SigSpec &dst)
auto make_buffer_f = [&](IdString type, const SigSpec &src, const SigSpec &dst)
{
auto it = old_buffers.find(pair<IdString, SigSpec>(type, dst));

2
passes/techmap/simplemap.cc
View file

@ -27,7 +27,7 @@
USING_YOSYS_NAMESPACE
YOSYS_NAMESPACE_BEGIN
static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) {
static void transfer_attr (Cell* to, const Cell* from, IdString attr) {
if (from->has_attribute(attr))
to->attributes[attr] = from->attributes.at(attr);
}