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Merge pull request #5341 from rocallahan/more-varargs-conversion

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More varargs conversion
This commit is contained in:
Jannis Harder 2025-09-12 18:09:42 +02:00 • committed by GitHub
commit 193b057983
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GPG key ID: B5690EEEBB952194
9 changed files with 156 additions and 168 deletions
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76
backends/btor/btor.cc
View file

@ -102,20 +102,16 @@ struct BtorWorker
PrettyJson ywmap_json;
void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
template <typename... Args>
void btorf(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
va_list ap;
va_start(ap, fmt);
f << indent << vstringf(fmt, ap);
va_end(ap);
f << indent << fmt.format(args...);
}
void infof(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
template <typename... Args>
void infof(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
va_list ap;
va_start(ap, fmt);
info_lines.push_back(vstringf(fmt, ap));
va_end(ap);
info_lines.push_back(fmt.format(args...));
}
template<typename T>
@ -322,12 +318,12 @@ struct BtorWorker
btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
nid = next_nid++;
btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell));
}
else
{
nid = next_nid++;
btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -368,7 +364,7 @@ struct BtorWorker
int sid = get_bv_sid(width);
int nid = next_nid++;
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -394,12 +390,12 @@ struct BtorWorker
if (cell->type == ID($_ANDNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
}
if (cell->type == ID($_ORNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -421,13 +417,13 @@ struct BtorWorker
if (cell->type == ID($_OAI3_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
}
if (cell->type == ID($_AOI3_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -452,14 +448,14 @@ struct BtorWorker
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
}
if (cell->type == ID($_AOI4_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -491,9 +487,9 @@ struct BtorWorker
int nid = next_nid++;
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
} else {
btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -528,7 +524,7 @@ struct BtorWorker
log_assert(!btor_op.empty());
int sid = get_bv_sid(width);
nid = next_nid++;
btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
}
if (GetSize(sig) < width) {
@ -568,9 +564,9 @@ struct BtorWorker
int nid = next_nid++;
if (btor_op != "not")
btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
else
btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -601,11 +597,11 @@ struct BtorWorker
if (cell->type == ID($reduce_xnor)) {
int nid2 = next_nid++;
btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
btorf("%d not %d %d\n", nid2, sid, nid);
nid = nid2;
} else {
btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@ -640,9 +636,9 @@ struct BtorWorker
int tmp = nid;
nid = next_nid++;
btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell).c_str());
btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell));
} else {
btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell));
}
add_nid_sig(nid, sig_y);
@ -665,7 +661,7 @@ struct BtorWorker
int nid_s = get_sig_nid(sig_s.extract(i));
int nid2 = next_nid++;
if (i == GetSize(sig_s)-1)
btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell));
else
btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
nid = nid2;
@ -753,7 +749,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
btorf("%d state %d%s\n", nid, sid, getinfo(cell).c_str());
btorf("%d state %d%s\n", nid, sid, getinfo(cell));
ywmap_state(sig_y);
@ -776,7 +772,7 @@ struct BtorWorker
int one_nid = get_sig_nid(State::S1);
int zero_nid = get_sig_nid(State::S0);
initstate_nid = next_nid++;
btorf("%d state %d%s\n", initstate_nid, sid, getinfo(cell).c_str());
btorf("%d state %d%s\n", initstate_nid, sid, getinfo(cell));
btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
@ -1051,7 +1047,7 @@ struct BtorWorker
if (consts.count(c) == 0) {
int sid = get_bv_sid(GetSize(c));
int nid = next_nid++;
btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
btorf("%d const %d %s\n", nid, sid, c.as_string());
consts[c] = nid;
nid_width[nid] = GetSize(c);
}
@ -1215,7 +1211,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig));
int nid = next_nid++;
btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str());
btorf("%d input %d%s\n", nid, sid, getinfo(wire));
ywmap_input(wire);
add_nid_sig(nid, sig);
@ -1260,7 +1256,7 @@ struct BtorWorker
btorf_push(stringf("output %s", log_id(wire)));
int nid = get_sig_nid(wire);
btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire).c_str());
btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire));
btorf_pop(stringf("output %s", log_id(wire)));
}
@ -1302,10 +1298,10 @@ struct BtorWorker
bad_properties.push_back(nid_en_and_not_a);
} else {
if (cover_mode) {
infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true));
} else {
int nid = next_nid++;
btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true));
}
}
@ -1327,7 +1323,7 @@ struct BtorWorker
bad_properties.push_back(nid_en_and_a);
} else {
int nid = next_nid++;
btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true));
}
btorf_pop(log_id(cell));
@ -1348,7 +1344,7 @@ struct BtorWorker
continue;
int this_nid = next_nid++;
btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire));
if (info_clocks.count(nid))
info_clocks[this_nid] |= info_clocks[nid];
@ -1371,7 +1367,7 @@ struct BtorWorker
SigSpec sig = sigmap(cell->getPort(ID::D));
int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig));
btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell));
btorf_pop(stringf("next %s", log_id(cell)));
}
@ -1430,7 +1426,7 @@ struct BtorWorker
}
int nid2 = next_nid++;
btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, (mem->cell ? getinfo(mem->cell) : getinfo(mem->mem)).c_str());
btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, (mem->cell ? getinfo(mem->cell) : getinfo(mem->mem)));
btorf_pop(stringf("next %s", log_id(mem->memid)));
}

12
frontends/ast/ast.cc
View file

@ -193,7 +193,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
auto& attr = attributes.at(id);
if (attr->type != AST_CONSTANT)
attr->input_error("Attribute `%s' with non-constant value!\n", id.c_str());
attr->input_error("Attribute `%s' with non-constant value!\n", id);
return attr->integer != 0;
}
@ -1143,7 +1143,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
{
for (auto& node : ast->children)
if (node->type == AST_PARAMETER && param_has_no_default(node.get()))
node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str());
node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str);
bool blackbox_module = flag_lib;
@ -1256,7 +1256,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
for (auto &attr : ast->attributes) {
log_assert((bool)attr.second.get());
if (attr.second->type != AST_CONSTANT)
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first);
module->attributes[attr.first] = attr.second->asAttrConst();
}
for (size_t i = 0; i < ast->children.size(); i++) {
@ -1922,11 +1922,9 @@ void AstModule::loadconfig() const
flag_autowire = autowire;
}
void AstNode::input_error(const char *format, ...) const
void AstNode::formatted_input_error(std::string str) const
{
va_list ap;
va_start(ap, format);
logv_file_error(*location.begin.filename, location.begin.line, format, ap);
log_formatted_file_error(*location.begin.filename, location.begin.line, std::move(str));
}
YOSYS_NAMESPACE_END

7
frontends/ast/ast.h
View file

@ -378,7 +378,12 @@ namespace AST
AstNode *get_struct_member() const;
// helper to print errors from simplify/genrtlil code
[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));
[[noreturn]] void formatted_input_error(std::string str) const;
template <typename... Args>
[[noreturn]] void input_error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args) const
{
formatted_input_error(fmt.format(args...));
}
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code

68
frontends/ast/genrtlil.cc
View file

@ -56,7 +56,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
if (gen_attributes)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -88,7 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
if (that != nullptr)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -114,7 +114,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -149,7 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -352,7 +352,7 @@ struct AST_INTERNAL::ProcessGenerator
set_src_attr(proc, always.get());
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
always->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
always->input_error("Attribute `%s' with non-constant value!\n", attr.first);
proc->attributes[attr.first] = attr.second->asAttrConst();
}
current_case = &proc->root_case;
@ -630,7 +630,7 @@ struct AST_INTERNAL::ProcessGenerator
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first);
sw->attributes[attr.first] = attr.second->asAttrConst();
}
@ -1007,7 +1007,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
}
}
if (!id_ast)
input_error("Failed to resolve identifier %s for width detection!\n", str.c_str());
input_error("Failed to resolve identifier %s for width detection!\n", str);
if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
@ -1017,7 +1017,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (id_ast->children[0]->type == AST_CONSTANT)
this_width = id_ast->children[0]->bits.size();
else
input_error("Failed to detect width for parameter %s!\n", str.c_str());
input_error("Failed to detect width for parameter %s!\n", str);
}
if (children.size() != 0)
range = children[0].get();
@ -1030,7 +1030,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// log("---\n");
// id_ast->dumpAst(nullptr, "decl> ");
// dumpAst(nullptr, "ref> ");
input_error("Failed to detect width of signal access `%s'!\n", str.c_str());
input_error("Failed to detect width of signal access `%s'!\n", str);
}
} else {
this_width = id_ast->range_left - id_ast->range_right + 1;
@ -1041,7 +1041,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = 32;
} else if (id_ast->type == AST_MEMORY) {
if (!id_ast->children[0]->range_valid)
input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
input_error("Failed to detect width of memory access `%s'!\n", str);
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
if (children.size() > 1)
range = children[1].get();
@ -1049,7 +1049,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
auto tmp_range = make_index_range(id_ast);
this_width = tmp_range->range_left - tmp_range->range_right + 1;
} else
input_error("Failed to detect width for identifier %s!\n", str.c_str());
input_error("Failed to detect width for identifier %s!\n", str);
if (range) {
if (range->children.size() == 1)
this_width = 1;
@ -1059,7 +1059,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
} else
this_width = range->range_left - range->range_right + 1;
@ -1193,7 +1193,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (!id2ast->is_signed)
sign_hint = false;
if (!id2ast->children[0]->range_valid)
input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
input_error("Failed to detect width of memory access `%s'!\n", str);
this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
width_hint = max(width_hint, this_width);
break;
@ -1266,7 +1266,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// item expressions.
const AstNode *func = current_scope.at(str);
if (func->type != AST_FUNCTION)
input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str());
input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str));
const AstNode *wire = nullptr;
for (const auto& child : func->children)
if (child->str == func->str) {
@ -1302,7 +1302,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
for (auto f : log_files)
current_scope_ast->dumpAst(f, "verilog-ast> ");
input_error("Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
input_error("Don't know how to detect sign and width for %s node!\n", type2str(type));
}
@ -1406,7 +1406,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (flag_pwires)
{
if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT)
input_error("Parameter `%s' with non-constant value!\n", str.c_str());
input_error("Parameter `%s' with non-constant value!\n", str);
RTLIL::Const val = children[0]->bitsAsConst();
RTLIL::IdString id = str;
@ -1420,7 +1420,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
wire->attributes[attr.first] = attr.second->asAttrConst();
}
}
@ -1429,10 +1429,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: {
if (!range_valid)
input_error("Signal `%s' with non-constant width!\n", str.c_str());
input_error("Signal `%s' with non-constant width!\n", str);
if (!(range_left + 1 >= range_right))
input_error("Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
input_error("Signal `%s' with invalid width range %d!\n", str, range_left - range_right + 1);
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "signal");
@ -1448,7 +1448,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
wire->attributes[attr.first] = attr.second->asAttrConst();
}
@ -1464,7 +1464,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_assert(children[1]->type == AST_RANGE);
if (!children[0]->range_valid || !children[1]->range_valid)
input_error("Memory `%s' with non-constant width or size!\n", str.c_str());
input_error("Memory `%s' with non-constant width or size!\n", str);
RTLIL::Memory *memory = new RTLIL::Memory;
set_src_attr(memory, this);
@ -1482,7 +1482,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
memory->attributes[attr.first] = attr.second->asAttrConst();
}
}
@ -1539,11 +1539,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} else if (flag_autowire)
log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str());
else
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str);
}
else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) {
if (id2ast->children[0]->type != AST_CONSTANT)
input_error("Parameter %s does not evaluate to constant value!\n", str.c_str());
input_error("Parameter %s does not evaluate to constant value!\n", str);
chunk = RTLIL::Const(id2ast->children[0]->bits);
goto use_const_chunk;
}
@ -1558,11 +1558,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
is_interface = true;
}
else {
input_error("Identifier `%s' doesn't map to any signal!\n", str.c_str());
input_error("Identifier `%s' doesn't map to any signal!\n", str);
}
if (id2ast->type == AST_MEMORY)
input_error("Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
input_error("Identifier `%s' does map to an unexpanded memory!\n", str);
// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
@ -1610,7 +1610,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
auto fake_ast = std::make_unique<AstNode>(children[0]->location, AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone());
@ -2032,7 +2032,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
set_src_attr(cell, this);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
cell->setParam(ID(FLAVOR), flavor);
@ -2148,7 +2148,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value.\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value.\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
if (cell->type == ID($specify2)) {
@ -2203,7 +2203,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_warning(*location.begin.filename, location.begin.line, "\n");
} else if (str == "$error") {
if (sz > 0)
input_error("%s.\n", children[0]->str.c_str());
input_error("%s.\n", children[0]->str);
else
input_error("\n");
} else if (str == "$fatal") {
@ -2212,11 +2212,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// dollar_finish(sz ? children[0] : 1);
// perhaps create & use log_file_fatal()
if (sz > 0)
input_error("FATAL: %s.\n", children[0]->str.c_str());
input_error("FATAL: %s.\n", children[0]->str);
else
input_error("FATAL.\n");
} else {
input_error("Unknown elaboration system task '%s'.\n", str.c_str());
input_error("Unknown elaboration system task '%s'.\n", str);
}
} break;
@ -2245,7 +2245,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (width <= 0)
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
Cell *cell = current_module->addCell(myid, str.substr(1));
set_src_attr(cell, this);
@ -2272,7 +2272,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
default:
for (auto f : log_files)
current_ast_mod->dumpAst(f, "verilog-ast> ");
input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str());
input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type));
}
return RTLIL::SigSpec();

84
frontends/ast/simplify.cc
View file

@ -250,7 +250,7 @@ static int range_width(AstNode *node, AstNode *rnode)
{
log_assert(rnode->type==AST_RANGE);
if (!rnode->range_valid) {
node->input_error("Non-constant range in declaration of %s\n", node->str.c_str());
node->input_error("Non-constant range in declaration of %s\n", node->str);
}
// note: range swapping has already been checked for
return rnode->range_left - rnode->range_right + 1;
@ -265,7 +265,7 @@ static int add_dimension(AstNode *node, AstNode *rnode)
[[noreturn]] static void struct_array_packing_error(AstNode *node)
{
node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str());
node->input_error("Unpacked array in packed struct/union member %s\n", node->str);
}
static int size_packed_struct(AstNode *snode, int base_offset)
@ -358,7 +358,7 @@ static int size_packed_struct(AstNode *snode, int base_offset)
}
else {
if (packed_width != width)
node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width);
node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str, width, packed_width);
}
}
else {
@ -481,7 +481,7 @@ std::unique_ptr<AstNode> AstNode::make_index_range(AstNode *decl_node, bool unpa
dim--; // Step back to the final index / slice
}
else {
input_error("Unsupported range operation for %s\n", str.c_str());
input_error("Unsupported range operation for %s\n", str);
}
std::unique_ptr<AstNode> index_range = std::make_unique<AstNode>(rnode->location, AST_RANGE);
@ -1135,7 +1135,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode.get();
else
input_error("enum item %s already exists in current scope\n", enode->str.c_str());
input_error("enum item %s already exists in current scope\n", enode->str);
}
}
}
@ -1209,7 +1209,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
continue;
wires_are_incompatible:
if (stage > 1)
input_error("Incompatible re-declaration of wire %s.\n", node->str.c_str());
input_error("Incompatible re-declaration of wire %s.\n", node->str);
continue;
}
this_wire_scope[node->str] = node;
@ -1228,7 +1228,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode.get();
else
input_error("enum item %s already exists\n", enode->str.c_str());
input_error("enum item %s already exists\n", enode->str);
}
}
}
@ -1268,7 +1268,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode.get();
else
input_error("enum item %s already exists in package\n", enode->str.c_str());
input_error("enum item %s already exists in package\n", enode->str);
}
}
}
@ -1561,10 +1561,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
const std::string &type_name = child->children[0]->str;
if (!current_scope.count(type_name))
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
input_error("Unknown identifier `%s' used as type name\n", type_name);
AstNode *resolved_type_node = current_scope.at(type_name);
if (resolved_type_node->type != AST_TYPEDEF)
input_error("`%s' does not name a type\n", type_name.c_str());
input_error("`%s' does not name a type\n", type_name);
log_assert(resolved_type_node->children.size() == 1);
auto* template_node = resolved_type_node->children[0].get();
@ -1909,7 +1909,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (pos == std::string::npos)
input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str());
input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname));
paramname = "\\" + paramname.substr(pos+1);
@ -1943,11 +1943,11 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
log_assert(children[0]->type == AST_WIRETYPE);
auto type_name = children[0]->str;
if (!current_scope.count(type_name)) {
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
input_error("Unknown identifier `%s' used as type name\n", type_name);
}
AstNode *resolved_type_node = current_scope.at(type_name);
if (resolved_type_node->type != AST_TYPEDEF)
input_error("`%s' does not name a type\n", type_name.c_str());
input_error("`%s' does not name a type\n", type_name);
log_assert(resolved_type_node->children.size() == 1);
auto& template_node = resolved_type_node->children[0];
@ -1985,7 +1985,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
// Cannot add packed dimensions if unpacked dimensions are already specified.
if (add_packed_dimensions && newNode->type == AST_MEMORY)
input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name.c_str());
input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name);
// Add packed dimensions.
if (add_packed_dimensions) {
@ -2030,7 +2030,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
children.insert(children.begin(), std::move(expr));
if (children[1]->type == AST_MEMORY)
input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());
input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str);
fixup_hierarchy_flags();
did_something = true;
}
@ -2331,7 +2331,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (current_scope.count(str) == 0) {
if (current_ast_mod == nullptr) {
input_error("Identifier `%s' is implicitly declared outside of a module.\n", str.c_str());
input_error("Identifier `%s' is implicitly declared outside of a module.\n", str);
} else if (flag_autowire || str == "\\$global_clock") {
auto auto_wire = std::make_unique<AstNode>(location, AST_AUTOWIRE);
auto_wire->str = str;
@ -2339,7 +2339,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
current_ast_mod->children.push_back(std::move(auto_wire));
did_something = true;
} else {
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str);
}
}
if (id2ast != current_scope[str]) {
@ -2562,7 +2562,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (buf->type != AST_CONSTANT)
input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str());
input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type));
varbuf->children[0] = std::move(buf);
}
@ -2778,7 +2778,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (type == AST_PRIMITIVE)
{
if (children.size() < 2)
input_error("Insufficient number of arguments for primitive `%s'!\n", str.c_str());
input_error("Insufficient number of arguments for primitive `%s'!\n", str);
std::vector<std::unique_ptr<AstNode>> children_list;
for (auto& child : children) {
@ -2792,7 +2792,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
{
if (children_list.size() != 3)
input_error("Invalid number of arguments for primitive `%s'!\n", str.c_str());
input_error("Invalid number of arguments for primitive `%s'!\n", str);
std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
@ -2894,7 +2894,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
auto& range = children[0]->children[0];
if (!try_determine_range_width(range.get(), result_width))
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
if (range->children.size() >= 2)
shift_expr = range->children[1]->clone();
@ -3285,7 +3285,7 @@ skip_dynamic_range_lvalue_expansion:;
int width;
if (!try_determine_range_width(the_range.get(), width))
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
if (the_range->children.size() >= 2)
offset_ast = the_range->children[1]->clone();
@ -3405,7 +3405,7 @@ skip_dynamic_range_lvalue_expansion:;
auto buf = children[1]->clone();
while (buf->simplify(true, stage, -1, false)) { }
if (buf->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str);
num_steps = buf->asInt(true);
}
@ -3516,7 +3516,7 @@ skip_dynamic_range_lvalue_expansion:;
auto buf = children[0]->clone();
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
if (buf->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str);
RTLIL::Const arg_value = buf->bitsAsConst();
if (arg_value.as_bool())
@ -3563,7 +3563,7 @@ skip_dynamic_range_lvalue_expansion:;
if (id_ast == nullptr && current_scope.count(buf->str))
id_ast = current_scope.at(buf->str);
if (!id_ast)
input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
input_error("Failed to resolve identifier %s for width detection!\n", buf->str);
if (id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) {
// Check for item in packed struct / union
@ -3578,7 +3578,7 @@ skip_dynamic_range_lvalue_expansion:;
// TODO: IEEE Std 1800-2017 20.7: "If the first argument to an array query function would cause $dimensions to return 0
// or if the second argument is out of range, then 'x shall be returned."
if (dim < 1 || dim > dims)
input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str.c_str(), dims);
input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str, dims);
expr_dimensions = dims - dim + 1;
expr_unpacked_dimensions = std::max(id_ast->unpacked_dimensions - dim + 1, 0);
@ -3712,9 +3712,9 @@ skip_dynamic_range_lvalue_expansion:;
auto& node = children[i];
while (node->simplify(true, stage, -1, false)) { }
if (node->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str);
if (node->bits.size() != 1)
input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str);
control_bits.push_back(node->bits[0]);
}
@ -3817,7 +3817,7 @@ skip_dynamic_range_lvalue_expansion:;
if (current_scope.count(str) == 0)
str = try_pop_module_prefix();
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
input_error("Can't resolve function name `%s'.\n", str.c_str());
input_error("Can't resolve function name `%s'.\n", str);
}
if (type == AST_TCALL)
@ -3825,9 +3825,9 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "$finish" || str == "$stop")
{
if (!current_always || current_always->type != AST_INITIAL)
input_error("System task `%s' outside initial block is unsupported.\n", str.c_str());
input_error("System task `%s' outside initial block is unsupported.\n", str);
input_error("System task `%s' executed.\n", str.c_str());
input_error("System task `%s' executed.\n", str);
}
if (str == "\\$readmemh" || str == "\\$readmemb")
@ -3839,12 +3839,12 @@ skip_dynamic_range_lvalue_expansion:;
auto node_filename = children[0]->clone();
while (node_filename->simplify(true, stage, width_hint, sign_hint)) { }
if (node_filename->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str);
auto node_memory = children[1]->clone();
while (node_memory->simplify(true, stage, width_hint, sign_hint)) { }
if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str);
int start_addr = -1, finish_addr = -1;
@ -3852,7 +3852,7 @@ skip_dynamic_range_lvalue_expansion:;
auto node_addr = children[2]->clone();
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
if (node_addr->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str);
start_addr = int(node_addr->asInt(false));
}
@ -3860,7 +3860,7 @@ skip_dynamic_range_lvalue_expansion:;
auto node_addr = children[3]->clone();
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
if (node_addr->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str);
finish_addr = int(node_addr->asInt(false));
}
@ -3888,7 +3888,7 @@ skip_dynamic_range_lvalue_expansion:;
if (current_scope.count(str) == 0)
str = try_pop_module_prefix();
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
input_error("Can't resolve task name `%s'.\n", str.c_str());
input_error("Can't resolve task name `%s'.\n", str);
}
@ -3928,7 +3928,7 @@ skip_dynamic_range_lvalue_expansion:;
if (in_param)
input_error("Non-constant function call in constant expression.\n");
if (require_const_eval)
input_error("Function %s can only be called with constant arguments.\n", str.c_str());
input_error("Function %s can only be called with constant arguments.\n", str);
}
size_t arg_count = 0;
@ -4050,7 +4050,7 @@ skip_dynamic_range_lvalue_expansion:;
goto tcall_incompatible_wires;
} else {
tcall_incompatible_wires:
input_error("Incompatible re-declaration of wire %s.\n", child->str.c_str());
input_error("Incompatible re-declaration of wire %s.\n", child->str);
}
}
}
@ -4476,7 +4476,7 @@ std::unique_ptr<AstNode> AstNode::readmem(bool is_readmemh, std::string mem_file
yosys_input_files.insert(mem_filename);
}
if (f.fail() || GetSize(mem_filename) == 0)
input_error("Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
input_error("Can not open file `%s` for %s.\n", mem_filename, str);
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right;
@ -4522,7 +4522,7 @@ std::unique_ptr<AstNode> AstNode::readmem(bool is_readmemh, std::string mem_file
char *endptr;
cursor = strtol(nptr, &endptr, 16);
if (!*nptr || *endptr)
input_error("Can not parse address `%s` for %s.\n", nptr, str.c_str());
input_error("Can not parse address `%s` for %s.\n", nptr, str);
continue;
}
@ -5421,7 +5421,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
// if this variable has already been declared as an input, check the
// sizes match if it already had an explicit size
if (variable.arg && variable.explicitly_sized && variable.val.size() != width) {
input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str());
input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str);
}
variable.val = RTLIL::Const(RTLIL::State::Sx, width);
variable.offset = stmt->range_swapped ? stmt->range_left : stmt->range_right;
@ -5503,7 +5503,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
if (!range->range_valid) {
if (!must_succeed)
goto finished;
range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str());
range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string());
}
int offset = min(range->range_left, range->range_right);
int width = std::abs(range->range_left - range->range_right) + 1;

35
frontends/verilog/verilog_error.cc
View file

@ -32,37 +32,14 @@ USING_YOSYS_NAMESPACE
*/
[[noreturn]]
static void verr_at(std::string filename, int begin_line, char const *fmt, va_list ap)
void VERILOG_FRONTEND::formatted_err_at_loc(Location loc, std::string str)
{
char buffer[1024];
char *p = buffer;
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_file_error(filename, begin_line, "%s", buffer);
exit(1);
YOSYS_NAMESPACE_PREFIX log_file_error(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line,
"%s\n", std::move(str));
}
static void vwarn_at(std::string filename, int begin_line, char const *fmt, va_list ap)
void VERILOG_FRONTEND::formatted_warn_at_loc(Location loc, std::string str)
{
char buffer[1024];
char *p = buffer;
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_file_warning(filename, begin_line, "%s", buffer);
YOSYS_NAMESPACE_PREFIX log_file_warning(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line,
"%s\n", std::move(str));
}
[[noreturn]]
void VERILOG_FRONTEND::err_at_loc(Location loc, char const *fmt, ...)
{
va_list args;
va_start(args, fmt);
verr_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args);
}
void VERILOG_FRONTEND::warn_at_loc(Location loc, char const *fmt, ...)
{
va_list args;
va_start(args, fmt);
vwarn_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args);
va_end(args);
}

16
frontends/verilog/verilog_error.h
View file

@ -10,8 +10,20 @@ YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND
{
[[noreturn]]
void err_at_loc(Location loc, char const *fmt, ...);
void warn_at_loc(Location loc, char const *fmt, ...);
void formatted_err_at_loc(Location loc, std::string str);
template <typename... Args>
[[noreturn]]
void err_at_loc(Location loc, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
formatted_err_at_loc(std::move(loc), fmt.format(args...));
}
void formatted_warn_at_loc(Location loc, std::string str);
template <typename... Args>
void warn_at_loc(Location loc, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
formatted_warn_at_loc(std::move(loc), fmt.format(args...));
}
};
YOSYS_NAMESPACE_END

2
frontends/verilog/verilog_frontend.cc
View file

@ -51,7 +51,7 @@ static std::list<std::vector<std::string>> verilog_defaults_stack;
static void error_on_dpi_function(AST::AstNode *node)
{
if (node->type == AST::AST_DPI_FUNCTION)
err_at_loc(node->location, "Found DPI function %s.\n", node->str.c_str());
err_at_loc(node->location, "Found DPI function %s.\n", node->str);
for (auto& child : node->children)
error_on_dpi_function(child.get());
}

24
frontends/verilog/verilog_parser.y
View file

@ -420,7 +420,7 @@
void frontend_verilog_yy::parser::error(const frontend_verilog_yy::parser::location_type& loc, const std::string& msg)
{
err_at_loc(loc, "%s", msg.c_str());
err_at_loc(loc, "%s", msg);
}
}
@ -772,7 +772,7 @@ module_arg:
extra->ast_stack.back()->children.push_back(std::move(node));
} else {
if (extra->port_stubs.count(*$1) != 0)
err_at_loc(@1, "Duplicate module port `%s'.", $1->c_str());
err_at_loc(@1, "Duplicate module port `%s'.", *$1);
extra->port_stubs[*$1] = ++extra->port_counter;
}
} module_arg_opt_assignment |
@ -782,7 +782,7 @@ module_arg:
extra->astbuf1->children[0]->str = *$1;
} TOK_ID { /* SV interfaces */
if (!mode->sv)
err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", *$3);
extra->astbuf2 = extra->astbuf1->clone(); // really only needed if multiple instances of same type.
extra->astbuf2->str = *$3;
extra->astbuf2->port_id = ++extra->port_counter;
@ -797,9 +797,9 @@ module_arg:
if (range != nullptr)
node->children.push_back(std::move(range));
if (!node->is_input && !node->is_output)
err_at_loc(@4, "Module port `%s' is neither input nor output.", $4->c_str());
err_at_loc(@4, "Module port `%s' is neither input nor output.", *$4);
if (node->is_reg && node->is_input && !node->is_output && !mode->sv)
err_at_loc(@4, "Input port `%s' is declared as register.", $4->c_str());
err_at_loc(@4, "Input port `%s' is declared as register.", *$4);
append_attr(node.get(), std::move($1));
extra->ast_stack.back()->children.push_back(std::move(node));
} module_arg_opt_assignment |
@ -1381,7 +1381,7 @@ specify_item:
TOK_ID TOK_LPAREN specify_edge expr specify_condition TOK_COMMA specify_edge expr specify_condition TOK_COMMA specify_triple specify_opt_triple TOK_RPAREN TOK_SEMICOL {
if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
*$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
err_at_loc(@1, "Unsupported specify rule type: %s", $1->c_str());
err_at_loc(@1, "Unsupported specify rule type: %s", *$1);
auto src_pen = AstNode::mkconst_int(@3, $3 != 0, false, 1);
auto src_pol = AstNode::mkconst_int(@3, $3 == 'p', false, 1);
@ -2156,21 +2156,21 @@ wire_name:
node->port_id = extra->current_function_or_task_port_id++;
} else if (extra->ast_stack.back()->type == AST_GENBLOCK) {
if (node->is_input || node->is_output)
err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", $1->c_str());
err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", *$1);
} else {
if (extra->do_not_require_port_stubs && (node->is_input || node->is_output) && extra->port_stubs.count(*$1) == 0) {
extra->port_stubs[*$1] = ++extra->port_counter;
}
if (extra->port_stubs.count(*$1) != 0) {
if (!node->is_input && !node->is_output)
err_at_loc(@1, "Module port `%s' is neither input nor output.", $1->c_str());
err_at_loc(@1, "Module port `%s' is neither input nor output.", *$1);
if (node->is_reg && node->is_input && !node->is_output && !mode->sv)
err_at_loc(@1, "Input port `%s' is declared as register.", $1->c_str());
err_at_loc(@1, "Input port `%s' is declared as register.", *$1);
node->port_id = extra->port_stubs[*$1];
extra->port_stubs.erase(*$1);
} else {
if (node->is_input || node->is_output)
err_at_loc(@1, "Module port `%s' is not declared in module header.", $1->c_str());
err_at_loc(@1, "Module port `%s' is not declared in module header.", *$1);
}
}
//FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
@ -3247,7 +3247,7 @@ basic_expr:
} |
TOK_LPAREN expr TOK_RPAREN integral_number {
if ($4->compare(0, 1, "'") != 0)
err_at_loc(@4, "Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
err_at_loc(@4, "Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", *$4);
ConstParser p{@4};
auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
if (val == nullptr)
@ -3256,7 +3256,7 @@ basic_expr:
} |
hierarchical_id integral_number {
if ($2->compare(0, 1, "'") != 0)
err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", *$2);
auto bits = std::make_unique<AstNode>(@$, AST_IDENTIFIER);
bits->str = *$1;
SET_AST_NODE_LOC(bits.get(), @1, @1);