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Merge pull request #5341 from rocallahan/more-varargs-conversion

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More varargs conversion
This commit is contained in:
Jannis Harder 2025-09-12 18:09:42 +02:00 • committed by GitHub
commit 193b057983
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GPG key ID: B5690EEEBB952194
9 changed files with 156 additions and 168 deletions
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35
frontends/verilog/verilog_error.cc
View file

@ -32,37 +32,14 @@ USING_YOSYS_NAMESPACE
*/
[[noreturn]]
static void verr_at(std::string filename, int begin_line, char const *fmt, va_list ap)
void VERILOG_FRONTEND::formatted_err_at_loc(Location loc, std::string str)
{
char buffer[1024];
char *p = buffer;
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_file_error(filename, begin_line, "%s", buffer);
exit(1);
YOSYS_NAMESPACE_PREFIX log_file_error(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line,
"%s\n", std::move(str));
}
static void vwarn_at(std::string filename, int begin_line, char const *fmt, va_list ap)
void VERILOG_FRONTEND::formatted_warn_at_loc(Location loc, std::string str)
{
char buffer[1024];
char *p = buffer;
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_file_warning(filename, begin_line, "%s", buffer);
YOSYS_NAMESPACE_PREFIX log_file_warning(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line,
"%s\n", std::move(str));
}
[[noreturn]]
void VERILOG_FRONTEND::err_at_loc(Location loc, char const *fmt, ...)
{
va_list args;
va_start(args, fmt);
verr_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args);
}
void VERILOG_FRONTEND::warn_at_loc(Location loc, char const *fmt, ...)
{
va_list args;
va_start(args, fmt);
vwarn_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args);
va_end(args);
}

16
frontends/verilog/verilog_error.h
View file

@ -10,8 +10,20 @@ YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND
{
[[noreturn]]
void err_at_loc(Location loc, char const *fmt, ...);
void warn_at_loc(Location loc, char const *fmt, ...);
void formatted_err_at_loc(Location loc, std::string str);
template <typename... Args>
[[noreturn]]
void err_at_loc(Location loc, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
formatted_err_at_loc(std::move(loc), fmt.format(args...));
}
void formatted_warn_at_loc(Location loc, std::string str);
template <typename... Args>
void warn_at_loc(Location loc, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
formatted_warn_at_loc(std::move(loc), fmt.format(args...));
}
};
YOSYS_NAMESPACE_END

2
frontends/verilog/verilog_frontend.cc
View file

@ -51,7 +51,7 @@ static std::list<std::vector<std::string>> verilog_defaults_stack;
static void error_on_dpi_function(AST::AstNode *node)
{
if (node->type == AST::AST_DPI_FUNCTION)
err_at_loc(node->location, "Found DPI function %s.\n", node->str.c_str());
err_at_loc(node->location, "Found DPI function %s.\n", node->str);
for (auto& child : node->children)
error_on_dpi_function(child.get());
}

24
frontends/verilog/verilog_parser.y
View file

@ -420,7 +420,7 @@
void frontend_verilog_yy::parser::error(const frontend_verilog_yy::parser::location_type& loc, const std::string& msg)
{
err_at_loc(loc, "%s", msg.c_str());
err_at_loc(loc, "%s", msg);
}
}
@ -772,7 +772,7 @@ module_arg:
extra->ast_stack.back()->children.push_back(std::move(node));
} else {
if (extra->port_stubs.count(*$1) != 0)
err_at_loc(@1, "Duplicate module port `%s'.", $1->c_str());
err_at_loc(@1, "Duplicate module port `%s'.", *$1);
extra->port_stubs[*$1] = ++extra->port_counter;
}
} module_arg_opt_assignment |
@ -782,7 +782,7 @@ module_arg:
extra->astbuf1->children[0]->str = *$1;
} TOK_ID { /* SV interfaces */
if (!mode->sv)
err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", *$3);
extra->astbuf2 = extra->astbuf1->clone(); // really only needed if multiple instances of same type.
extra->astbuf2->str = *$3;
extra->astbuf2->port_id = ++extra->port_counter;
@ -797,9 +797,9 @@ module_arg:
if (range != nullptr)
node->children.push_back(std::move(range));
if (!node->is_input && !node->is_output)
err_at_loc(@4, "Module port `%s' is neither input nor output.", $4->c_str());
err_at_loc(@4, "Module port `%s' is neither input nor output.", *$4);
if (node->is_reg && node->is_input && !node->is_output && !mode->sv)
err_at_loc(@4, "Input port `%s' is declared as register.", $4->c_str());
err_at_loc(@4, "Input port `%s' is declared as register.", *$4);
append_attr(node.get(), std::move($1));
extra->ast_stack.back()->children.push_back(std::move(node));
} module_arg_opt_assignment |
@ -1381,7 +1381,7 @@ specify_item:
TOK_ID TOK_LPAREN specify_edge expr specify_condition TOK_COMMA specify_edge expr specify_condition TOK_COMMA specify_triple specify_opt_triple TOK_RPAREN TOK_SEMICOL {
if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
*$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
err_at_loc(@1, "Unsupported specify rule type: %s", $1->c_str());
err_at_loc(@1, "Unsupported specify rule type: %s", *$1);
auto src_pen = AstNode::mkconst_int(@3, $3 != 0, false, 1);
auto src_pol = AstNode::mkconst_int(@3, $3 == 'p', false, 1);
@ -2156,21 +2156,21 @@ wire_name:
node->port_id = extra->current_function_or_task_port_id++;
} else if (extra->ast_stack.back()->type == AST_GENBLOCK) {
if (node->is_input || node->is_output)
err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", $1->c_str());
err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", *$1);
} else {
if (extra->do_not_require_port_stubs && (node->is_input || node->is_output) && extra->port_stubs.count(*$1) == 0) {
extra->port_stubs[*$1] = ++extra->port_counter;
}
if (extra->port_stubs.count(*$1) != 0) {
if (!node->is_input && !node->is_output)
err_at_loc(@1, "Module port `%s' is neither input nor output.", $1->c_str());
err_at_loc(@1, "Module port `%s' is neither input nor output.", *$1);
if (node->is_reg && node->is_input && !node->is_output && !mode->sv)
err_at_loc(@1, "Input port `%s' is declared as register.", $1->c_str());
err_at_loc(@1, "Input port `%s' is declared as register.", *$1);
node->port_id = extra->port_stubs[*$1];
extra->port_stubs.erase(*$1);
} else {
if (node->is_input || node->is_output)
err_at_loc(@1, "Module port `%s' is not declared in module header.", $1->c_str());
err_at_loc(@1, "Module port `%s' is not declared in module header.", *$1);
}
}
//FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
@ -3247,7 +3247,7 @@ basic_expr:
} |
TOK_LPAREN expr TOK_RPAREN integral_number {
if ($4->compare(0, 1, "'") != 0)
err_at_loc(@4, "Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
err_at_loc(@4, "Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", *$4);
ConstParser p{@4};
auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
if (val == nullptr)
@ -3256,7 +3256,7 @@ basic_expr:
} |
hierarchical_id integral_number {
if ($2->compare(0, 1, "'") != 0)
err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", *$2);
auto bits = std::make_unique<AstNode>(@$, AST_IDENTIFIER);
bits->str = *$1;
SET_AST_NODE_LOC(bits.get(), @1, @1);