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erase, clear, fork replace, idk

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This commit is contained in:
Emil J. Tywoniak 2024-06-13 20:31:11 +02:00
parent cc10ef7019
commit 193a43e82c
13 changed files with 134 additions and 69 deletions
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3
passes/fsm/fsm_extract.cc
View file

@ -395,7 +395,8 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size());
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
auto &x = cell->connections_[cellport.second];
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), x);
}
}

3
passes/fsm/fsmdata.h
View file

@ -48,7 +48,8 @@ struct FsmData
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
auto thing = cell->parameters[ID::STATE_TABLE];
std::vector<RTLIL::State> &bits_table = thing.bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}