erase, clear, fork replace, idk

passes/cmds/sta.cc

@@ -21,6 +21,7 @@
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/timinginfo.h"
+#include "kernel/compat.h"
 #include <deque>
 
 USING_YOSYS_NAMESPACE
@@ -74,7 +75,7 @@ struct StaWorker
 				continue;
 			}
 
-			IdString derived_type = inst_module->derive(design, cell->parameters);
+			IdString derived_type = inst_module->derive(design, cell_to_mod_params(cell->parameters));
 			inst_module = design->module(derived_type);
 			log_assert(inst_module);
 

passes/equiv/equiv_struct.cc

@@ -162,7 +162,7 @@ struct EquivStructWorker
 			Cell *cell = module->cell(cell_name);
 			key.type = cell->type;
 
-			for (auto &it : cell->parameters)
+			for (auto &&it : cell->parameters)
 				key.parameters.push_back(it);
 			std::sort(key.parameters.begin(), key.parameters.end());
 

passes/fsm/fsm_extract.cc

@@ -395,7 +395,8 @@ static void extract_fsm(RTLIL::Wire *wire)
 		RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size());
-		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
+		auto &x = cell->connections_[cellport.second];
+		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), x);
 	}
 }
 

passes/fsm/fsmdata.h

@@ -48,7 +48,8 @@ struct FsmData
 		cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
 
 		for (int i = 0; i < int(state_table.size()); i++) {
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
+			auto thing = cell->parameters[ID::STATE_TABLE];
+			std::vector<RTLIL::State> &bits_table = thing.bits;
 			std::vector<RTLIL::State> &bits_state = state_table[i].bits;
 			bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
 		}

passes/hierarchy/hierarchy.cc

@@ -19,6 +19,7 @@
  */
 
 #include "kernel/yosys.h"
+#include "kernel/compat.h"
 #include "frontends/verific/verific.h"
 #include <stdlib.h>
 #include <stdio.h>
@@ -69,7 +70,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 						portnames.insert(conn.first);
 					portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
 				}
-				for (auto &para : cell->parameters)
+				for (auto &&para : cell->parameters)
 					parameters.insert(para.first);
 			}
 
@@ -334,7 +335,7 @@ RTLIL::Module *get_module(RTLIL::Design                  &design,
 	std::string cell_type = cell.type.str();
 	RTLIL::Module *abs_mod = design.module("$abstract" + cell_type);
 	if (abs_mod) {
-		cell.type = abs_mod->derive(&design, cell.parameters);
+		cell.type = abs_mod->derive(&design, cell_to_mod_params(cell.parameters));
 		cell.parameters.clear();
 		RTLIL::Module *mod = design.module(cell.type);
 		log_assert(mod);
@@ -418,7 +419,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
 			          log_id(conn.first));
 		}
 	}
-	for (auto &param : cell.parameters) {
+	for (auto param : cell.parameters) {
 		if (read_id_num(param.first, &id)) {
 			if (id <= 0 || id > GetSize(mod.avail_parameters))
 				log_error("Module `%s' referenced in module `%s' in cell `%s' "
@@ -528,7 +529,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 		}
 
 		cell->type = mod->derive(design,
-					 cell->parameters,
+					 cell_to_mod_params(cell->parameters),
 					 if_expander.interfaces_to_add_to_submodule,
 					 if_expander.modports_used_in_submodule);
 		cell->parameters.clear();
@@ -1237,7 +1238,7 @@ struct HierarchyPass : public Pass {
 
 				// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
 				if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
-					IdString new_m_name = m->derive(design, cell->parameters, true);
+					IdString new_m_name = m->derive(design, cell_to_mod_params(cell->parameters), true);
 					if (new_m_name.empty())
 						continue;
 					if (new_m_name != m->name) {
@@ -1420,7 +1421,7 @@ struct HierarchyPass : public Pass {
 					continue;
 
 				if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
-					IdString new_m_name = m->derive(design, cell->parameters, true);
+					IdString new_m_name = m->derive(design, cell_to_mod_params(cell->parameters), true);
 					if (new_m_name.empty())
 						continue;
 					if (new_m_name != m->name) {

passes/hierarchy/submod.cc

@@ -208,7 +208,7 @@ struct SubmodWorker
 
 		for (RTLIL::Cell *cell : submod.cells) {
 			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
-			for (auto &conn : new_cell->connections_)
+			for (auto conn : new_cell->connections_)
 				for (auto &bit : conn.second)
 					if (bit.wire != nullptr) {
 						log_assert(wire_flags.count(bit.wire) > 0);

passes/opt/opt_merge.cc

@@ -140,7 +140,7 @@ struct OptMergeWorker
 			hash_conn_strings.push_back(s + "\n");
 		}
 
-		for (auto &it : cell->parameters)
+		for (auto &&it : cell->parameters)
 			hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
 
 		std::sort(hash_conn_strings.begin(), hash_conn_strings.end());

passes/techmap/abc9_ops.cc

@@ -23,6 +23,7 @@
 #include "kernel/utils.h"
 #include "kernel/celltypes.h"
 #include "kernel/timinginfo.h"
+#include "kernel/compat.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -113,7 +114,7 @@ void check(RTLIL::Design *design, bool dff_mode)
 					//   but not its existence)
 					if (!inst_module->has_attribute(ID::abc9_flop))
 						continue;
-					derived_type = inst_module->derive(design, cell->parameters);
+					derived_type = inst_module->derive(design, cell_to_mod_params(cell->parameters));
 					derived_module = design->module(derived_type);
 					log_assert(derived_module);
 				}
@@ -170,7 +171,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 				derived_module = inst_module;
 			}
 			else {
-				derived_type = inst_module->derive(design, cell->parameters);
+				derived_type = inst_module->derive(design, cell_to_mod_params(cell->parameters));
 				derived_module = design->module(derived_type);
 				unused_derived.insert(derived_type);
 			}