3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-24 08:24:35 +00:00

analogdevices: Extra tests

`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
This commit is contained in:
Krystine Sherwin 2025-10-18 17:38:01 +13:00
parent c0d68506ed
commit 18d1ba7f1f
No known key found for this signature in database
6 changed files with 211 additions and 13 deletions

View file

@ -1,4 +1,5 @@
#!/usr/bin/env bash
set -eu
python3 mem_gen.py
source ../../gen-tests-makefile.sh
generate_mk --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
generate_mk --yosys-scripts --bash