mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-21 14:50:33 +00:00
Code Activity

analogdevices: Extra tests

Browse source 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
This commit is contained in:
Krystine Sherwin 2025-10-18 17:38:01 +13:00
parent c0d68506ed
commit 18d1ba7f1f
No known key found for this signature in database
6 changed files with 211 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

1
Makefile
View file

@ -869,6 +869,7 @@ endif
# Tests that generate .mk with tests/gen-tests-makefile.sh
MK_TEST_DIRS =
MK_TEST_DIRS += tests/arch/analogdevices
MK_TEST_DIRS += tests/arch/anlogic
MK_TEST_DIRS += tests/arch/ecp5
MK_TEST_DIRS += tests/arch/efinix