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Massive performance improvement from refactoring RTLIL::SigSpec::optimize()

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This commit is contained in:
Clifford Wolf 2013-11-22 04:41:20 +01:00
parent 8e58bb330d
commit 18d003254c
1 changed files with 13 additions and 30 deletions
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43
kernel/rtlil.cc
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@ -981,37 +981,20 @@ void RTLIL::SigSpec::expand()
void RTLIL::SigSpec::optimize() void RTLIL::SigSpec::optimize()
{ {
for (size_t i = 0; i < chunks.size(); i++) { std::vector<RTLIL::SigChunk> new_chunks;
if (chunks[i].wire && chunks[i].wire->auto_width) for (auto &c : chunks)
continue; if (new_chunks.size() == 0) {
if (chunks[i].width == 0) new_chunks.push_back(c);
chunks.erase(chunks.begin()+i--); } else {
} RTLIL::SigChunk &cc = new_chunks.back();
for (size_t i = 1; i < chunks.size(); i++) { if (c.wire == NULL && cc.wire == NULL)
RTLIL::SigChunk &ch1 = chunks[i-1]; cc.data.bits.insert(cc.data.bits.end(), c.data.bits.begin(), c.data.bits.end());
RTLIL::SigChunk &ch2 = chunks[i]; if (c.wire == cc.wire && (c.wire == NULL || cc.offset + cc.width == c.offset))
if (ch1.wire && ch1.wire->auto_width) cc.width += c.width;
continue; else
if (ch2.wire && ch2.wire->auto_width) new_chunks.push_back(c);
continue;
if (ch1.wire == ch2.wire) {
if (ch1.wire != NULL && ch1.offset+ch1.width == ch2.offset) {
ch1.width += ch2.width;
goto merged_with_next_chunk;
}
if (ch1.wire == NULL && ch1.data.str.empty() == ch2.data.str.empty()) {
ch1.data.str = ch2.data.str + ch1.data.str;
ch1.data.bits.insert(ch1.data.bits.end(), ch2.data.bits.begin(), ch2.data.bits.end());
ch1.width += ch2.width;
goto merged_with_next_chunk;
}
}
if (0) {
merged_with_next_chunk:
chunks.erase(chunks.begin()+i);
i--;
}
} }
chunks.swap(new_chunks);
check(); check();
} }