mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
Don't be too smart with $dff cells with "init" attribute on out signal
This commit is contained in:
parent
66eb254fc2
commit
18cb8b4636
|
@ -83,7 +83,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
|
||||||
val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
|
val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
|
if (dff->type == "$dff" && mux_drivers.has(sig_d) && !has_init) {
|
||||||
std::set<RTLIL::Cell*> muxes;
|
std::set<RTLIL::Cell*> muxes;
|
||||||
mux_drivers.find(sig_d, muxes);
|
mux_drivers.find(sig_d, muxes);
|
||||||
for (auto mux : muxes) {
|
for (auto mux : muxes) {
|
||||||
|
|
Loading…
Reference in a new issue