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	xilinx_srl to use 'slice' features of pmgen for word level
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					 2 changed files with 49 additions and 32 deletions
				
			
		|  | @ -105,13 +105,15 @@ void run_variable(xilinx_srl_pm &pm) | ||||||
| 
 | 
 | ||||||
| 	log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); | 	log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); | ||||||
| 
 | 
 | ||||||
| 	auto last_cell = ud.chain.back(); | 	auto last_cell = ud.chain.back().first; | ||||||
| 
 | 
 | ||||||
| 	SigSpec initval; | 	SigSpec initval; | ||||||
| 	for (auto cell : ud.chain) { | 	for (const auto &i : ud.chain) { | ||||||
|  | 		auto cell = i.first; | ||||||
|  | 		auto slice = i.second; | ||||||
| 		log_debug("    %s\n", log_id(cell)); | 		log_debug("    %s\n", log_id(cell)); | ||||||
| 		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { | 		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { | ||||||
| 			SigBit Q = cell->getPort(ID(Q)); | 			SigBit Q = cell->getPort(ID(Q))[slice]; | ||||||
| 			log_assert(Q.wire); | 			log_assert(Q.wire); | ||||||
| 			auto it = Q.wire->attributes.find(ID(init)); | 			auto it = Q.wire->attributes.find(ID(init)); | ||||||
| 			if (it != Q.wire->attributes.end()) { | 			if (it != Q.wire->attributes.end()) { | ||||||
|  | @ -123,7 +125,7 @@ void run_variable(xilinx_srl_pm &pm) | ||||||
| 		else | 		else | ||||||
| 			log_abort(); | 			log_abort(); | ||||||
| 		if (cell != last_cell) | 		if (cell != last_cell) | ||||||
| 			pm.autoremove(cell); | 			cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID); | ||||||
| 	} | 	} | ||||||
| 	pm.autoremove(st.shiftx); | 	pm.autoremove(st.shiftx); | ||||||
| 
 | 
 | ||||||
|  | @ -131,23 +133,36 @@ void run_variable(xilinx_srl_pm &pm) | ||||||
| 	SigBit Q = st.first->getPort(ID(Q)); | 	SigBit Q = st.first->getPort(ID(Q)); | ||||||
| 	c->setPort(ID(Q), Q); | 	c->setPort(ID(Q), Q); | ||||||
| 
 | 
 | ||||||
| 	if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { | 	if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { | ||||||
| 		c->parameters.clear(); | 		Const clkpol, enpol; | ||||||
| 		c->setParam(ID(DEPTH), GetSize(ud.chain)); |  | ||||||
| 		c->setParam(ID(INIT), initval.as_const()); |  | ||||||
| 		if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) | 		if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) | ||||||
| 			c->setParam(ID(CLKPOL), 1); | 			clkpol = 1; | ||||||
| 		else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) | 		else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_))) | ||||||
| 			c->setParam(ID(CLKPOL), 0); | 			clkpol = 0; | ||||||
|  | 		else if (c->type.in(ID($dff), ID($dffe))) { | ||||||
|  | 			clkpol = c->getParam(ID(CLK_POLARITY)); | ||||||
|  | 			c->setPort(ID(C), c->getPort(ID(CLK))); | ||||||
|  | 			c->unsetPort(ID(CLK)); | ||||||
|  | 		} | ||||||
| 		else | 		else | ||||||
| 			log_abort(); | 			log_abort(); | ||||||
| 		if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) | 		if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) | ||||||
| 			c->setParam(ID(ENPOL), 1); | 			enpol = 1; | ||||||
| 		else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) | 		else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) | ||||||
| 			c->setParam(ID(ENPOL), 0); | 			enpol = 0; | ||||||
|  | 		else if (c->type.in(ID($dffe))) { | ||||||
|  | 			enpol = c->getParam(ID(EN_POLARITY)); | ||||||
|  | 			c->setPort(ID(E), c->getPort(ID(EN))); | ||||||
|  | 			c->unsetPort(ID(EN)); | ||||||
|  | 		} | ||||||
| 		else | 		else | ||||||
| 			c->setParam(ID(ENPOL), 2); | 			enpol = 2; | ||||||
| 		if (c->type.in(ID($_DFF_N_), ID($_DFF_P_))) | 		c->parameters.clear(); | ||||||
|  | 		c->setParam(ID(DEPTH), GetSize(ud.chain)); | ||||||
|  | 		c->setParam(ID(INIT), initval.as_const()); | ||||||
|  | 		c->setParam(ID(CLKPOL), clkpol); | ||||||
|  | 		c->setParam(ID(ENPOL), enpol); | ||||||
|  | 		if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) | ||||||
| 			c->setPort(ID(E), State::S1); | 			c->setPort(ID(E), State::S1); | ||||||
| 		c->setPort(ID(L), st.shiftx->getPort(ID(B))); | 		c->setPort(ID(L), st.shiftx->getPort(ID(B))); | ||||||
| 		c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); | 		c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); | ||||||
|  |  | ||||||
|  | @ -151,8 +151,9 @@ endcode | ||||||
| pattern variable | pattern variable | ||||||
| 
 | 
 | ||||||
| state <int> shiftx_width | state <int> shiftx_width | ||||||
|  | state <int> slice | ||||||
| udata <int> minlen | udata <int> minlen | ||||||
| udata <vector<Cell*>> chain | udata <vector<pair<Cell*,int>>> chain | ||||||
| 
 | 
 | ||||||
| match shiftx | match shiftx | ||||||
| 	select shiftx->type.in($shiftx) | 	select shiftx->type.in($shiftx) | ||||||
|  | @ -166,13 +167,16 @@ code shiftx_width | ||||||
| endcode | endcode | ||||||
| 
 | 
 | ||||||
| match first | match first | ||||||
| 	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) | 	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) | ||||||
| 	select nusers(port(first, \Q)) == 2 | 	select !first->has_keep_attr() | ||||||
| 	index <SigBit> port(first, \Q) === port(shiftx, \A)[shiftx_width-1] | 	slice idx GetSize(port(first, \Q)) | ||||||
|  | 	select nusers(port(first, \Q)[idx]) == 2 | ||||||
|  | 	index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] | ||||||
|  | 	set slice idx | ||||||
| endmatch | endmatch | ||||||
| 
 | 
 | ||||||
| code | code | ||||||
| 	chain.push_back(first); | 	chain.emplace_back(first, slice); | ||||||
| 	subpattern(tail); | 	subpattern(tail); | ||||||
| finally | finally | ||||||
| 	if (GetSize(chain) == shiftx_width) | 	if (GetSize(chain) == shiftx_width) | ||||||
|  | @ -185,26 +189,24 @@ endcode | ||||||
| subpattern tail | subpattern tail | ||||||
| arg shiftx | arg shiftx | ||||||
| arg shiftx_width | arg shiftx_width | ||||||
|  | arg slice | ||||||
| 
 | 
 | ||||||
| match next | match next | ||||||
| 	semioptional | 	semioptional | ||||||
| 	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) | 	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) | ||||||
| 	select !next->has_keep_attr() | 	select !next->has_keep_attr() | ||||||
| 	select !port(next, \D)[0].wire->get_bool_attribute(\keep) | 	select !port(next, \D)[0].wire->get_bool_attribute(\keep) | ||||||
| 	select nusers(port(next, \Q)) == 3 | 	slice idx GetSize(port(next, \Q)) | ||||||
| 	index <IdString> next->type === chain.back()->type | 	select nusers(port(next, \Q)[idx]) == 3 | ||||||
| 	index <SigBit> port(next, \Q) === port(chain.back(), \D) | 	index <IdString> next->type === chain.back().first->type | ||||||
| 	index <SigBit> port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] | 	index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] | ||||||
|  | 	index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] | ||||||
|  | 	set slice idx | ||||||
| endmatch | endmatch | ||||||
| 
 | 
 | ||||||
| code | code | ||||||
| 	if (next) { | 	if (next) { | ||||||
| 		auto sig = port(next, \Q); | 		chain.emplace_back(next, slice); | ||||||
| 		log_warning("nusers of '%s'\n", log_signal(sig)); |  | ||||||
| 		for (auto bit : sigmap(sig)) |  | ||||||
| 			for (auto user : sigusers[bit]) |  | ||||||
| 				log_warning("\t%s\n", log_id(user)); |  | ||||||
| 		chain.push_back(next); |  | ||||||
| 		if (GetSize(chain) < shiftx_width) | 		if (GetSize(chain) < shiftx_width) | ||||||
| 			subpattern(tail); | 			subpattern(tail); | ||||||
| 	} | 	} | ||||||
|  |  | ||||||
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