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Add #1135 testcase

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This commit is contained in:
Eddie Hung 2019-06-27 11:02:52 -07:00
parent 7c14678ec0
commit 18acb72c05
2 changed files with 25 additions and 4 deletions
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10
tests/various/pmux2shiftx.v
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@ -32,3 +32,13 @@ module pmux2shiftx_test (
endcase endcase
end end
endmodule endmodule
module issue01135(input [7:0] i, output o);
always @*
case (i[6:3])
4: o <= i[0];
3: o <= i[2];
7: o <= i[3];
default: o <= 1'b0;
endcase
endmodule

19
tests/various/pmux2shiftx.ys
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@ -1,4 +1,7 @@
read_verilog pmux2shiftx.v read_verilog pmux2shiftx.v
design -save read
hierarchy -top pmux2shiftx_test
prep prep
design -save gold design -save gold
@ -21,8 +24,16 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load gold #design -load gold
stat #stat
#
#design -load gate
#stat
design -load gate design -load read
stat hierarchy -top issue01135
proc
pmux2shiftx -norange
opt -full
select -assert-count 0 t:$shift*
select -assert-count 1 t:$pmux