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https://github.com/YosysHQ/yosys
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opt_clean: refactor
This commit is contained in:
Emil J. Tywoniak
parent
17688f053b
commit
187e91ad65
1 changed files with 144 additions and 121 deletions
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@ -659,7 +659,7 @@ static InitBits consume_inits(ShardedVector<RTLIL::Wire*> &initialized_wires, co
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}
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struct SigAnalysis {
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// `register_signals` and `connected_signals` will help us decide later on
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// `registers` and `connected` will help us decide later on
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// on picking representatives out of groups of connected signals
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// Wire bits driven by registers (with clk2fflogic exception)
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@ -790,6 +790,135 @@ struct UsedSigAnalysis {
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}
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};
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struct WireDeleter {
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pool<RTLIL::Wire*> del_wires_queue;
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ShardedVector<RTLIL::Wire*> remove_init;
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ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_init;
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ShardedVector<RTLIL::SigSig> connections;
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ShardedVector<RTLIL::Wire*> remove_unused_bits;
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ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_unused_bits;
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WireDeleter(UsedSigAnalysis& used_sig_analysis, bool purge_mode, const RTLIL::Module* mod, SigMap& assign_map, ParallelDispatchThreadPool::Subpool &subpool) :
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remove_init(subpool),
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set_init(subpool),
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connections(subpool),
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remove_unused_bits(subpool),
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set_unused_bits(subpool) {
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ShardedVector<RTLIL::Wire*> del_wires(subpool);
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subpool.run([mod, purge_mode, &del_wires, &assign_map, &used_sig_analysis, this](const ParallelDispatchThreadPool::RunCtx &ctx) {
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for (int i : ctx.item_range(mod->wires_size())) {
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RTLIL::Wire *wire = mod->wire_at(i);
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SigSpec s1 = SigSpec(wire), s2 = assign_map(s1);
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log_assert(GetSize(s1) == GetSize(s2));
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Const initval;
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bool has_init_attribute = wire->attributes.count(ID::init);
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bool init_changed = false;
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if (has_init_attribute)
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initval = wire->attributes.at(ID::init);
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if (GetSize(initval) != GetSize(wire)) {
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initval.resize(GetSize(wire), State::Sx);
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init_changed = true;
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}
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if (GetSize(wire) == 0) {
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// delete zero-width wires, unless they are module ports
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if (wire->port_id == 0)
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goto delete_this_wire;
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} else
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if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
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// do not delete anything with "keep" or module ports or initialized wires
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} else
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if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_used, s1) || check_any(used_sig_analysis.used, s2) || s1 != s2)) {
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// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
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} else
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if (!check_any(used_sig_analysis.raw_used, s1)) {
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// delete wires that aren't used by anything directly
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goto delete_this_wire;
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}
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if (0)
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{
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delete_this_wire:
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del_wires.insert(ctx, wire);
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}
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else
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{
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RTLIL::SigSig new_conn;
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for (int i = 0; i < GetSize(s1); i++)
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if (s1[i] != s2[i]) {
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if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
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s2[i] = initval[i];
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initval.set(i, State::Sx);
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init_changed = true;
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}
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new_conn.first.append(s1[i]);
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new_conn.second.append(s2[i]);
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}
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if (new_conn.first.size() > 0)
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connections.insert(ctx, std::move(new_conn));
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if (initval.is_fully_undef()) {
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if (has_init_attribute)
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remove_init.insert(ctx, wire);
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} else
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if (init_changed)
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set_init.insert(ctx, {wire, std::move(initval)});
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std::string unused_bits;
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if (!check_all(used_sig_analysis.used_nodrivers, s2)) {
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for (int i = 0; i < GetSize(s2); i++) {
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if (s2[i].wire == NULL)
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continue;
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SigBit b = s2[i];
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if (used_sig_analysis.used_nodrivers.find({b, b.hash_top().yield()}) == nullptr) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%d", i);
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}
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}
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}
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if (unused_bits.empty() || wire->port_id != 0) {
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if (wire->attributes.count(ID::unused_bits))
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remove_unused_bits.insert(ctx, wire);
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} else {
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RTLIL::Const unused_bits_const(std::move(unused_bits));
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if (wire->attributes.count(ID::unused_bits)) {
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RTLIL::Const &unused_bits_attr = wire->attributes.at(ID::unused_bits);
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if (unused_bits_attr != unused_bits_const)
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set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
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} else
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set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
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}
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}
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}
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});
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del_wires_queue.insert(del_wires.begin(), del_wires.end());
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}
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// now decide for each wire if we should be deleting it
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void commit_attrs(RTLIL::Module* mod) {
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for (RTLIL::Wire *wire : remove_init)
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wire->attributes.erase(ID::init);
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for (auto &p : set_init)
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p.first->attributes[ID::init] = std::move(p.second);
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for (auto &conn : connections)
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mod->connect(std::move(conn));
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for (RTLIL::Wire *wire : remove_unused_bits)
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wire->attributes.erase(ID::unused_bits);
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for (auto &p : set_unused_bits)
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p.first->attributes[ID::unused_bits] = std::move(p.second);
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}
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int delete_wires(RTLIL::Module* mod, bool verbose) {
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int deleted_and_unreported = 0;
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for (auto wire : del_wires_queue) {
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if (ys_debug() || (check_public_name(wire->name) && verbose))
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log_debug(" removing unused non-port wire %s.\n", wire->name);
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else
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deleted_and_unreported++;
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}
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mod->remove(del_wires_queue);
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return deleted_and_unreported;
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}
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};
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bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool purge_mode, bool verbose, RmStats &stats)
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{
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SigMap assign_map(module);
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@ -832,142 +961,36 @@ bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::
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assign_map.add(candidate);
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}
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// we are removing all connections
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// Remove all wire-wire connections
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module->connections_.clear();
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UsedSigAnalysis used_sig_analysis(sig_analysis, const_module, assign_map, subpool);
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fixup_update_ports(used_sig_analysis.update_connections);
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consume_inits(used_sig_analysis.initialized_wires, assign_map).apply_normalised_inits();
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// now decide for each wire if we should be deleting it
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ShardedVector<RTLIL::Wire*> del_wires(subpool);
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ShardedVector<RTLIL::Wire*> remove_init(subpool);
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ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_init(subpool);
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ShardedVector<RTLIL::SigSig> connections(subpool);
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ShardedVector<RTLIL::Wire*> remove_unused_bits(subpool);
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ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_unused_bits(subpool);
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subpool.run([const_module, purge_mode, &assign_map, &used_sig_analysis, &del_wires, &remove_init, &set_init, &connections, &remove_unused_bits, &set_unused_bits](const ParallelDispatchThreadPool::RunCtx &ctx) {
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for (int i : ctx.item_range(const_module->wires_size())) {
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RTLIL::Wire *wire = const_module->wire_at(i);
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SigSpec s1 = SigSpec(wire), s2 = assign_map(s1);
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log_assert(GetSize(s1) == GetSize(s2));
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Const initval;
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bool has_init_attribute = wire->attributes.count(ID::init);
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bool init_changed = false;
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if (has_init_attribute)
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initval = wire->attributes.at(ID::init);
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if (GetSize(initval) != GetSize(wire)) {
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initval.resize(GetSize(wire), State::Sx);
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init_changed = true;
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}
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if (GetSize(wire) == 0) {
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// delete zero-width wires, unless they are module ports
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if (wire->port_id == 0)
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goto delete_this_wire;
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} else
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if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
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// do not delete anything with "keep" or module ports or initialized wires
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} else
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if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_used, s1) || check_any(used_sig_analysis.used, s2) || s1 != s2)) {
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// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
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} else
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if (!check_any(used_sig_analysis.raw_used, s1)) {
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// delete wires that aren't used by anything directly
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goto delete_this_wire;
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}
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if (0)
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{
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delete_this_wire:
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del_wires.insert(ctx, wire);
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}
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else
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{
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RTLIL::SigSig new_conn;
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for (int i = 0; i < GetSize(s1); i++)
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if (s1[i] != s2[i]) {
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if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
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s2[i] = initval[i];
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initval.set(i, State::Sx);
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init_changed = true;
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}
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new_conn.first.append(s1[i]);
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new_conn.second.append(s2[i]);
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}
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if (new_conn.first.size() > 0)
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connections.insert(ctx, std::move(new_conn));
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if (initval.is_fully_undef()) {
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if (has_init_attribute)
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remove_init.insert(ctx, wire);
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} else
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if (init_changed)
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set_init.insert(ctx, {wire, std::move(initval)});
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std::string unused_bits;
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if (!check_all(used_sig_analysis.used_nodrivers, s2)) {
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for (int i = 0; i < GetSize(s2); i++) {
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if (s2[i].wire == NULL)
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continue;
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SigBit b = s2[i];
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if (used_sig_analysis.used_nodrivers.find({b, b.hash_top().yield()}) == nullptr) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%d", i);
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}
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}
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}
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if (unused_bits.empty() || wire->port_id != 0) {
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if (wire->attributes.count(ID::unused_bits))
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remove_unused_bits.insert(ctx, wire);
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} else {
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RTLIL::Const unused_bits_const(std::move(unused_bits));
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if (wire->attributes.count(ID::unused_bits)) {
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RTLIL::Const &unused_bits_attr = wire->attributes.at(ID::unused_bits);
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if (unused_bits_attr != unused_bits_const)
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set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
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} else
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set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
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}
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}
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}
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});
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pool<RTLIL::Wire*> del_wires_queue;
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del_wires_queue.insert(del_wires.begin(), del_wires.end());
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for (RTLIL::Wire *wire : remove_init)
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wire->attributes.erase(ID::init);
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for (auto &p : set_init)
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p.first->attributes[ID::init] = std::move(p.second);
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for (auto &conn : connections)
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module->connect(std::move(conn));
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for (RTLIL::Wire *wire : remove_unused_bits)
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wire->attributes.erase(ID::unused_bits);
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for (auto &p : set_unused_bits)
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p.first->attributes[ID::unused_bits] = std::move(p.second);
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WireDeleter deleter(used_sig_analysis,
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purge_mode,
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const_module,
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assign_map,
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subpool);
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subpool.run([&used_sig_analysis](const ParallelDispatchThreadPool::RunCtx &ctx) {
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used_sig_analysis.clear(ctx);
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});
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int del_temp_wires_count = 0;
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for (auto wire : del_wires_queue) {
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if (ys_debug() || (check_public_name(wire->name) && verbose))
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log_debug(" removing unused non-port wire %s.\n", wire->name);
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else
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del_temp_wires_count++;
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}
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deleter.commit_attrs(module);
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int deleted_and_unreported = deleter.delete_wires(module, verbose);
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int deleted_total = GetSize(deleter.del_wires_queue);
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module->remove(del_wires_queue);
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stats.count_rm_wires += GetSize(del_wires_queue);
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stats.count_rm_wires += deleted_total;
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if (verbose && del_temp_wires_count)
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log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count);
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if (verbose && deleted_and_unreported)
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log_debug(" removed %d unused temporary wires.\n", deleted_and_unreported);
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if (!del_wires_queue.empty())
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if (deleted_total)
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module->design->scratchpad_set_bool("opt.did_something", true);
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return !del_wires_queue.empty();
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return deleted_total != 0;
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}
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bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
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