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Don't adjust naming on imported cells. Add $ for each pass

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This commit is contained in:
Akash Levy 2024-05-19 15:02:40 -07:00
parent 8086e132fb
commit 187737b86a
3 changed files with 4 additions and 7 deletions
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2
passes/opt/wreduce.cc
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@ -458,7 +458,7 @@ struct WreduceWorker
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
Wire *nw = module->addWire(IdString("$" + w->name.str()), GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}