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static cast: support changing size and signedness

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Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)

Fix #535
This commit is contained in:
Kazuki Sakamoto 2020-06-14 15:15:59 -07:00
parent 338ecbe02f
commit 185bbbe681
6 changed files with 48 additions and 0 deletions
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1
frontends/ast/simplify.cc
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@ -950,6 +950,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
case AST_TO_SIGNED:
case AST_TO_UNSIGNED:
case AST_SELFSZ:
case AST_CAST_SIZE:
case AST_CONCAT:
case AST_REPLICATE:
case AST_REDUCE_AND: