mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

$size() now works with memories as well!

Browse source
This commit is contained in:
Udi Finkelstein 2017-09-26 08:36:45 +03:00
parent 64eb8f29ad
commit 17f8b41605
2 changed files with 7 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
frontends/ast/simplify.cc
View file

@ -387,7 +387,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
for (size_t i = 0; i < children.size(); i++) {
AstNode *node = children[i];
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE)
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY)
while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
did_something = true;
}
@ -1877,6 +1877,8 @@ skip_dynamic_range_lvalue_expansion:;
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
AstNode *buf = children[0]->clone();
// Is this needed?
//while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
buf->detectSignWidth(width_hint, sign_hint);
delete buf;

6
tests/simple/functions01.sv
View file

@ -2,13 +2,15 @@ module functions01;
wire [3:0]x;
wire [$size(x)-1:0]x_size;
wire [$size({x, x})-1:0]xx_size;
wire [3:0]w[0:5];
wire [3:0]y[0:5];
wire [$size(y)-1:0]y_size;
wire [3:0]z[0:5][0:7];
wire [$size(z)-1:0]z_size;
//
// The following are not supported yet:
//
//wire [$size(w)-1:0]w_s;
//wire [$bits(x)-1:0]x_bits;
//wire [$bits({x, x})-1:0]xx_bits;