mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

opt_expr: restore consume_x; use for coarse grained too

Browse source
This commit is contained in:
Eddie Hung 2020-05-08 11:07:44 -07:00
parent 495acf9815
commit 17f4e06247
1 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
passes/opt/opt_expr.cc
View file

@ -543,13 +543,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
} }
if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef))) { if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef && consume_x))) {
cover("opt.opt_expr.const_and"); cover("opt.opt_expr.const_and");
replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0); replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0);
goto next_cell; goto next_cell;
} }
if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef))) { if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef && consume_x))) {
cover("opt.opt_expr.const_or"); cover("opt.opt_expr.const_or");
replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1); replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1);
goto next_cell; goto next_cell;
@ -927,7 +927,7 @@ skip_fine_alu:
if (input.match("**")) ACTION_DO_Y(x); if (input.match("**")) ACTION_DO_Y(x);
if (input.match("1*")) ACTION_DO_Y(x); if (input.match("1*")) ACTION_DO_Y(x);
if (input.match("*1")) ACTION_DO_Y(x); if (input.match("*1")) ACTION_DO_Y(x);
if (!keepdc) { if (consume_x) {
if (input.match(" *")) ACTION_DO_Y(0); if (input.match(" *")) ACTION_DO_Y(0);
if (input.match("* ")) ACTION_DO_Y(0); if (input.match("* ")) ACTION_DO_Y(0);
} }
@ -946,7 +946,7 @@ skip_fine_alu:
if (input.match("**")) ACTION_DO_Y(x); if (input.match("**")) ACTION_DO_Y(x);
if (input.match("0*")) ACTION_DO_Y(x); if (input.match("0*")) ACTION_DO_Y(x);
if (input.match("*0")) ACTION_DO_Y(x); if (input.match("*0")) ACTION_DO_Y(x);
if (!keepdc) { if (consume_x) {
if (input.match(" *")) ACTION_DO_Y(1); if (input.match(" *")) ACTION_DO_Y(1);
if (input.match("* ")) ACTION_DO_Y(1); if (input.match("* ")) ACTION_DO_Y(1);
} }
@ -963,7 +963,7 @@ skip_fine_alu:
if (input.match("01")) ACTION_DO_Y(1); if (input.match("01")) ACTION_DO_Y(1);
if (input.match("10")) ACTION_DO_Y(1); if (input.match("10")) ACTION_DO_Y(1);
if (input.match("11")) ACTION_DO_Y(0); if (input.match("11")) ACTION_DO_Y(0);
if (!keepdc) { if (consume_x) {
if (input.match(" *")) ACTION_DO_Y(0); if (input.match(" *")) ACTION_DO_Y(0);
if (input.match("* ")) ACTION_DO_Y(0); if (input.match("* ")) ACTION_DO_Y(0);
} }
@ -1149,7 +1149,7 @@ skip_fine_alu:
goto next_cell; goto next_cell;
} }
if (!keepdc) if (!keepdc && consume_x)
{ {
bool identity_wrt_a = false; bool identity_wrt_a = false;
bool identity_wrt_b = false; bool identity_wrt_b = false;