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abstract: -state MVP

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Emil J. Tywoniak 2025-01-30 17:26:23 +01:00
parent f445479374
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tests/various/abstract.ys Normal file
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read_verilog <<EOT
module half_clock (CLK, Q);
input CLK;
output reg Q;
reg magic;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
abstract -state -enablen magic
# show