mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
abstract: -state MVP
This commit is contained in:
parent
f445479374
commit
17b8b7352c
3 changed files with 124 additions and 0 deletions
14
tests/various/abstract.ys
Normal file
14
tests/various/abstract.ys
Normal file
|
@ -0,0 +1,14 @@
|
|||
read_verilog <<EOT
|
||||
|
||||
module half_clock (CLK, Q);
|
||||
input CLK;
|
||||
output reg Q;
|
||||
reg magic;
|
||||
always @(posedge CLK)
|
||||
Q <= ~Q;
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
proc
|
||||
abstract -state -enablen magic
|
||||
# show
|
Loading…
Add table
Add a link
Reference in a new issue