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Added support for SystemVerilog packages with localparam definitions

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This commit is contained in:
Ruben Undheim 2016-06-18 10:24:21 +02:00
parent 3380281e15
commit 178ff3e7f6
7 changed files with 53 additions and 1 deletions
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1
frontends/ast/genrtlil.cc
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@ -806,6 +806,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENBLOCK:
case AST_GENIF:
case AST_GENCASE:
case AST_PACKAGE:
break;
// remember the parameter, needed for example in techmap