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Added support for SystemVerilog packages with localparam definitions

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This commit is contained in:
Ruben Undheim 2016-06-18 10:24:21 +02:00
parent 3380281e15
commit 178ff3e7f6
7 changed files with 53 additions and 1 deletions
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12
frontends/ast/ast.cc
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@ -151,6 +151,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_POSEDGE)
X(AST_NEGEDGE)
X(AST_EDGE)
X(AST_PACKAGE)
#undef X
default:
log_abort();
@ -996,6 +997,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
for (auto n : global_decls)
(*it)->children.push_back(n->clone());
for (auto n : design->packages){
for (auto o : n->children) {
AstNode *cloned_node = o->clone();
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
(*it)->children.push_back(cloned_node);
}
}
if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
(*it)->str = (*it)->str.substr(1);
@ -1013,6 +1022,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
design->add(process_module(*it, defer));
}
else if ((*it)->type == AST_PACKAGE){
design->packages.push_back((*it)->clone());
}
else
global_decls.push_back(*it);
}

4
frontends/ast/ast.h
View file

@ -137,7 +137,9 @@ namespace AST
AST_POSEDGE,
AST_NEGEDGE,
AST_EDGE
AST_EDGE,
AST_PACKAGE
};
// convert an node type to a string (e.g. for debug output)

1
frontends/ast/genrtlil.cc
View file

@ -806,6 +806,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENBLOCK:
case AST_GENIF:
case AST_GENCASE:
case AST_PACKAGE:
break;
// remember the parameter, needed for example in techmap