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https://github.com/YosysHQ/yosys
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Add support for mockup clock signals in yosys-smtbmc vcd output
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
f2cfe73d74
commit
17583b6a21
3 changed files with 111 additions and 6 deletions
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@ -41,6 +41,8 @@ struct Smt2Worker
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std::set<RTLIL::Cell*> exported_cells, hiercells, hiercells_queue;
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pool<Cell*> recursive_cells, registers;
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pool<SigBit> clock_posedge, clock_negedge;
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std::map<RTLIL::SigBit, std::pair<int, int>> fcache;
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std::map<Cell*, int> memarrays;
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std::map<int, int> bvsizes;
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@ -104,18 +106,24 @@ struct Smt2Worker
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decls.push_back(decl_str + "\n");
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}
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Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose, bool statebv, bool statedt, dict<IdString, int> &mod_stbv_width) :
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Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose, bool statebv, bool statedt,
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dict<IdString, int> &mod_stbv_width, dict<IdString, dict<IdString, pair<bool, bool>>> &mod_clk_cache) :
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ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode), wiresmode(wiresmode),
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verbose(verbose), statebv(statebv), statedt(statedt), mod_stbv_width(mod_stbv_width), idcounter(0), statebv_width(0)
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{
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pool<SigBit> noclock;
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makebits(stringf("%s_is", get_id(module)));
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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for (auto &conn : cell->connections())
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{
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if (GetSize(conn.second) == 0)
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continue;
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bool is_input = ct.cell_input(cell->type, conn.first);
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bool is_output = ct.cell_output(cell->type, conn.first);
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if (is_output && !is_input)
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for (auto bit : sigmap(conn.second)) {
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if (bit_driver.count(bit))
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@ -125,6 +133,48 @@ struct Smt2Worker
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else if (is_output || !is_input)
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log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
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log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
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if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn.first.in("\\CLK", "\\C"))
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{
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bool posedge = (cell->type == "$_DFF_N_") || (cell->type == "$dff" && cell->getParam("\\CLK_POLARITY").as_bool());
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for (auto bit : sigmap(conn.second)) {
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if (posedge)
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clock_posedge.insert(bit);
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else
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clock_negedge.insert(bit);
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}
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}
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else
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if (mod_clk_cache.count(cell->type) && mod_clk_cache.at(cell->type).count(conn.first))
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{
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for (auto bit : sigmap(conn.second)) {
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if (mod_clk_cache.at(cell->type).at(conn.first).first)
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clock_posedge.insert(bit);
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if (mod_clk_cache.at(cell->type).at(conn.first).second)
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clock_negedge.insert(bit);
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}
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}
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else
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{
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for (auto bit : sigmap(conn.second))
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noclock.insert(bit);
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}
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}
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for (auto bit : noclock) {
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clock_posedge.erase(bit);
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clock_negedge.erase(bit);
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}
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for (auto wire : module->wires())
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{
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if (!wire->port_input || GetSize(wire) != 1)
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continue;
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SigBit bit = sigmap(wire);
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if (clock_posedge.count(bit))
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mod_clk_cache[module->name][wire->name].first = true;
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if (clock_negedge.count(bit))
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mod_clk_cache[module->name][wire->name].second = true;
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}
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}
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@ -731,6 +781,9 @@ struct Smt2Worker
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decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
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if (wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\'))
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decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
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if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
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decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
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clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : ""));
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if (bvmode && GetSize(sig) > 1) {
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
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get_id(module), get_id(wire), get_id(module), GetSize(sig), get_bv(sig).c_str()));
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@ -1386,6 +1439,7 @@ struct Smt2Backend : public Backend {
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}
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dict<IdString, int> mod_stbv_width;
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dict<IdString, dict<IdString, pair<bool, bool>>> mod_clk_cache;
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Module *topmod = design->top_module();
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std::string topmod_id;
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@ -1396,7 +1450,7 @@ struct Smt2Backend : public Backend {
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log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
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Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose, statebv, statedt, mod_stbv_width);
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Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose, statebv, statedt, mod_stbv_width, mod_clk_cache);
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worker.run();
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worker.write(*f);
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@ -589,7 +589,11 @@ def write_vcd_trace(steps_start, steps_stop, index):
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if n.startswith("$"):
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hidden_net = True
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if not hidden_net:
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edge = smt.net_clock(topmod, netpath)
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if edge is None:
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vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
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else:
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vcd.add_clock([topmod] + netpath, edge)
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path_list.append(netpath)
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mem_trace_data = dict()
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@ -53,6 +53,7 @@ class SmtModInfo:
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self.memories = dict()
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self.wires = set()
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self.wsize = dict()
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self.clocks = dict()
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self.cells = dict()
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self.asserts = dict()
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self.covers = dict()
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@ -404,6 +405,13 @@ class SmtIo:
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self.modinfo[self.curmod].wires.add(fields[2])
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self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
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if fields[1] == "yosys-smt2-clock":
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for edge in fields[3:]:
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if fields[2] not in self.modinfo[self.curmod].clocks:
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self.modinfo[self.curmod].clocks[fields[2]] = edge
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elif self.modinfo[self.curmod].clocks[fields[2]] != edge:
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self.modinfo[self.curmod].clocks[fields[2]] = "event"
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if fields[1] == "yosys-smt2-assert":
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self.modinfo[self.curmod].asserts["%s_a %s" % (self.curmod, fields[2])] = fields[3]
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@ -672,6 +680,17 @@ class SmtIo:
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assert net_path[-1] in self.modinfo[mod].wsize
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return self.modinfo[mod].wsize[net_path[-1]]
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def net_clock(self, mod, net_path):
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for i in range(len(net_path)-1):
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assert mod in self.modinfo
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assert net_path[i] in self.modinfo[mod].cells
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mod = self.modinfo[mod].cells[net_path[i]]
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assert mod in self.modinfo
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if net_path[-1] not in self.modinfo[mod].clocks:
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return None
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return self.modinfo[mod].clocks[net_path[-1]]
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def net_exists(self, mod, net_path):
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for i in range(len(net_path)-1):
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if mod not in self.modinfo: return False
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@ -823,6 +842,7 @@ class MkVcd:
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self.f = f
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self.t = -1
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self.nets = dict()
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self.clocks = dict()
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def add_net(self, path, width):
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path = tuple(path)
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@ -830,10 +850,18 @@ class MkVcd:
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key = "n%d" % len(self.nets)
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self.nets[path] = (key, width)
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def add_clock(self, path, edge):
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path = tuple(path)
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assert self.t == -1
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key = "n%d" % len(self.nets)
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self.nets[path] = (key, 1)
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self.clocks[path] = (key, edge)
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def set_net(self, path, bits):
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path = tuple(path)
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assert self.t >= 0
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assert path in self.nets
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if path not in self.clocks:
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print("b%s %s" % (bits, self.nets[path][0]), file=self.f)
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def set_time(self, t):
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@ -851,13 +879,32 @@ class MkVcd:
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print("$scope module %s $end" % path[len(scope)], file=self.f)
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scope.append(path[len(scope)-1])
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key, width = self.nets[path]
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if path in self.clocks and self.clocks[path][1] == "event":
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print("$var event 1 %s %s $end" % (key, path[-1]), file=self.f)
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else:
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print("$var wire %d %s %s $end" % (width, key, path[-1]), file=self.f)
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for i in range(len(scope)):
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print("$upscope $end", file=self.f)
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print("$enddefinitions $end", file=self.f)
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self.t = t
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assert self.t >= 0
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if self.t > 0:
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print("#%d" % (10 * self.t - 5), file=self.f)
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for path in sorted(self.clocks.keys()):
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if self.clocks[path][1] == "posedge":
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print("b0 %s" % self.nets[path][0], file=self.f)
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elif self.clocks[path][1] == "negedge":
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print("b1 %s" % self.nets[path][0], file=self.f)
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print("#%d" % (10 * self.t), file=self.f)
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print("1!", file=self.f)
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print("b%s t" % format(self.t, "032b"), file=self.f)
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for path in sorted(self.clocks.keys()):
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if self.clocks[path][1] == "negedge":
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print("b0 %s" % self.nets[path][0], file=self.f)
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else:
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print("b1 %s" % self.nets[path][0], file=self.f)
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