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Add support for mockup clock signals in yosys-smtbmc vcd output

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-02-20 17:45:22 +01:00
parent f2cfe73d74
commit 17583b6a21
3 changed files with 111 additions and 6 deletions
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6
backends/smt2/smtbmc.py
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@ -589,7 +589,11 @@ def write_vcd_trace(steps_start, steps_stop, index):
if n.startswith("$"):
hidden_net = True
if not hidden_net:
vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
edge = smt.net_clock(topmod, netpath)
if edge is None:
vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
else:
vcd.add_clock([topmod] + netpath, edge)
path_list.append(netpath)
mem_trace_data = dict()