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Update CHANGELOG and README

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Signed-off-by: David Shah <dave@ds0.me>
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David Shah 2019-09-20 13:01:47 +01:00
parent abc155715d
commit 1746b6373b
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1
CHANGELOG
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@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
- "synth_ice40 -dsp" to infer DSP blocks - "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx - Added latch support to synth_xilinx
- Added support for SystemVerilog typedefs
Yosys 0.8 .. Yosys 0.9 Yosys 0.8 .. Yosys 0.9
---------------------- ----------------------

2
README.md
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@ -510,6 +510,8 @@ from SystemVerilog:
into a design with ``read_verilog``, all its packages are available to into a design with ``read_verilog``, all its packages are available to
SystemVerilog files being read into the same design afterwards. SystemVerilog files being read into the same design afterwards.
- typedefs are supported (including inside packages)
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported. ports are inputs or outputs are supported.