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Add support for non-power-of-two mem chunks in verific importer

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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
This commit is contained in:
Claire Wolf 2020-05-14 14:38:13 +02:00
parent 27b7ffc754
commit 173aa27ca5
1 changed files with 12 additions and 2 deletions
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14
frontends/verific/verific.cc
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@ -1265,7 +1265,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
int numchunks = int(inst->OutputSize()) / memory->width; int numchunks = int(inst->OutputSize()) / memory->width;
int chunksbits = ceil_log2(numchunks); int chunksbits = ceil_log2(numchunks);
if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) if ((numchunks * memory->width) != int(inst->OutputSize()))
log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
for (int i = 0; i < numchunks; i++) for (int i = 0; i < numchunks; i++)
@ -1273,6 +1273,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
if ((numchunks & (numchunks - 1)) != 0) {
addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks));
addr = module->Add(NEW_ID, addr, RTLIL::Const(i));
}
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
cell->parameters[ID::MEMID] = memory->name.str(); cell->parameters[ID::MEMID] = memory->name.str();
@ -1295,7 +1300,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
int numchunks = int(inst->Input2Size()) / memory->width; int numchunks = int(inst->Input2Size()) / memory->width;
int chunksbits = ceil_log2(numchunks); int chunksbits = ceil_log2(numchunks);
if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) if ((numchunks * memory->width) != int(inst->Input2Size()))
log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
for (int i = 0; i < numchunks; i++) for (int i = 0; i < numchunks; i++)
@ -1303,6 +1308,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
if ((numchunks & (numchunks - 1)) != 0) {
addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks));
addr = module->Add(NEW_ID, addr, RTLIL::Const(i));
}
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
cell->parameters[ID::MEMID] = memory->name.str(); cell->parameters[ID::MEMID] = memory->name.str();