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Extract ice40_unlut pass from ice40_opt.
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
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parent
615b30bd29
commit
1719aa88ac
3 changed files with 109 additions and 13 deletions
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@ -33,7 +33,7 @@ static SigBit get_bit_or_zero(const SigSpec &sig)
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return sig[0];
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}
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static void run_ice40_opts(Module *module, bool unlut_mode)
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static void run_ice40_opts(Module *module)
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{
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pool<SigBit> optimized_co;
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vector<Cell*> sb_lut_cells;
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@ -95,9 +95,6 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
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inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
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sigmap.apply(inbits);
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if (unlut_mode)
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goto remap_lut;
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if (optimized_co.count(inbits[0])) goto remap_lut;
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if (optimized_co.count(inbits[1])) goto remap_lut;
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if (optimized_co.count(inbits[2])) goto remap_lut;
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@ -152,14 +149,10 @@ struct Ice40OptPass : public Pass {
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log(" opt_clean\n");
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log(" while <changed design>\n");
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log("\n");
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log("When called with the option -unlut, this command will transform all already\n");
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log("mapped SB_LUT4 cells back to logic.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string opt_expr_args = "-mux_undef -undriven";
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bool unlut_mode = false;
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log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
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log_push();
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@ -170,10 +163,6 @@ struct Ice40OptPass : public Pass {
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opt_expr_args += " -full";
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continue;
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}
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if (args[argidx] == "-unlut") {
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unlut_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -184,7 +173,7 @@ struct Ice40OptPass : public Pass {
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log_header(design, "Running ICE40 specific optimizations.\n");
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for (auto module : design->selected_modules())
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run_ice40_opts(module, unlut_mode);
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run_ice40_opts(module);
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Pass::call(design, "opt_expr " + opt_expr_args);
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Pass::call(design, "opt_merge");
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