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	Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
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					 23 changed files with 280 additions and 37 deletions
				
			
		|  | @ -109,7 +109,7 @@ struct statdata_t | |||
| 						ID($lut), ID($and), ID($or), ID($xor), ID($xnor), | ||||
| 						ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), | ||||
| 						ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), | ||||
| 						ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) { | ||||
| 						ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor), ID($pow), ID($alu))) { | ||||
| 					int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0; | ||||
| 					int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0; | ||||
| 					int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0; | ||||
|  |  | |||
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