mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-14 13:41:27 +00:00
Code Activity

Add flooring modulo operator

Browse source 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
This commit is contained in:
Xiretza 2020-04-08 19:30:47 +02:00
parent 0d99522b3c
commit 17163cf43a
No known key found for this signature in database
GPG key ID: 17B78226F7139993
23 changed files with 280 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/btor/test_cells.sh
View file

@ -6,7 +6,7 @@ rm -rf test_cells.tmp
mkdir -p test_cells.tmp
cd test_cells.tmp
../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod'
../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod /$modfloor'
for fn in test_*.il; do
../../../yosys -p "