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Add abc9_ops -prep_dff
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parent
88b9c8d46d
commit
16c4ec7eda
3 changed files with 50 additions and 39 deletions
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@ -19,6 +19,7 @@
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -95,6 +96,44 @@ void unbreak_scc(RTLIL::Module *module) {
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module->fixup_ports();
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}
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void prep_dff(RTLIL::Module *module) {
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auto design = module->design;
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log_assert(design);
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SigMap assign_map(module);
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typedef SigSpec clkdomain_t;
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dict<clkdomain_t, int> clk_to_mergeability;
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for (auto cell : module->selected_cells()) {
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auto inst_module = design->module(cell->type);
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if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
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|| cell->get_bool_attribute("\\abc9_keep"))
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continue;
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Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
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if (abc9_clock_wire == NULL)
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log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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SigSpec abc9_clock = assign_map(abc9_clock_wire);
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clkdomain_t key(abc9_clock);
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auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
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auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
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log_assert(r2.second);
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Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
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if (abc9_init_wire == NULL)
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log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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log_assert(GetSize(abc9_init_wire) == 1);
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SigSpec abc9_init = assign_map(abc9_init_wire);
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if (!abc9_init.is_fully_const())
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log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
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log_assert(r2.second);
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}
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}
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struct Abc9PrepPass : public Pass {
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Abc9PrepPass() : Pass("abc9_ops", "helper functions for ABC9") { }
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void help() YS_OVERRIDE
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@ -111,6 +150,7 @@ struct Abc9PrepPass : public Pass {
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bool break_scc_mode = false;
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bool unbreak_scc_mode = false;
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bool prep_dff_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -123,6 +163,10 @@ struct Abc9PrepPass : public Pass {
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unbreak_scc_mode = true;
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continue;
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}
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if (arg == "-prep_dff") {
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prep_dff_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -132,6 +176,8 @@ struct Abc9PrepPass : public Pass {
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break_scc(mod);
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if (unbreak_scc_mode)
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unbreak_scc(mod);
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if (prep_dff_mode)
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prep_dff(mod);
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}
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}
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} Abc9PrepPass;
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