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Add abc9_ops -prep_dff
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3 changed files with 50 additions and 39 deletions
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@ -960,48 +960,13 @@ struct Abc9MapPass : public Pass {
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}
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}
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SigMap assign_map;
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CellTypes ct(design);
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for (auto module : design->selected_modules())
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{
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if (module->processes.size() > 0)
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log_error("Module '%s' has processes!\n", log_id(module));
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assign_map.set(module);
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typedef SigSpec clkdomain_t;
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dict<clkdomain_t, int> clk_to_mergeability;
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const std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
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for (auto cell : all_cells) {
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auto inst_module = design->module(cell->type);
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if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
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|| cell->get_bool_attribute("\\abc9_keep"))
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continue;
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Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
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if (abc9_clock_wire == NULL)
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log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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SigSpec abc9_clock = assign_map(abc9_clock_wire);
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clkdomain_t key(abc9_clock);
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auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
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auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
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log_assert(r2.second);
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Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
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if (abc9_init_wire == NULL)
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log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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log_assert(GetSize(abc9_init_wire) == 1);
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SigSpec abc9_init = assign_map(abc9_init_wire);
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if (!abc9_init.is_fully_const())
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log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
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log_assert(r2.second);
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}
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design->selected_active_module = module->name.str();
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abc9_module(design, module, script_file, exe_file, lut_costs,
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delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
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