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Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign

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peepopt.muldiv: Add a signedness check.
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clairexen 2020-08-20 16:19:37 +02:00 • committed by GitHub
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read_verilog <<EOT
module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
wire [7:0] P = A * B;
wire signed [7:0] SP = P;
wire signed [3:0] SB = B;
assign Y = SP / SB;
endmodule
EOT
equiv_opt -assert peepopt