diff --git a/Makefile b/Makefile
index bbed712bf..359ba6175 100644
--- a/Makefile
+++ b/Makefile
@@ -8,10 +8,6 @@ CONFIG := none
 # CONFIG := msys2-32
 # CONFIG := msys2-64
 
-# silimate features and settings
-ENABLE_SLANG := 1
-DISABLE_MEM_INIT := 1 # does not preserve logic equivalence!
-
 # features (the more the better)
 ENABLE_TCL := 0
 ENABLE_ABC := 0
@@ -20,6 +16,7 @@ ENABLE_PLUGINS := 0
 ENABLE_READLINE := 0
 ENABLE_EDITLINE := 1
 ENABLE_GHDL := 0
+ENABLE_SLANG := 1
 ENABLE_VERIFIC := 1
 ENABLE_VERIFIC_SYSTEMVERILOG := 1
 ENABLE_VERIFIC_VHDL := 0
@@ -491,10 +488,6 @@ endif
 endif
 endif
 
-ifeq ($(DISABLE_MEM_INIT),1)
-CXXFLAGS += -DSILIMATE_DISABLE_MEM_INIT
-endif
-
 ifeq ($(ENABLE_GHDL),1)
 GHDL_PREFIX ?= $(PREFIX)
 GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include
diff --git a/kernel/mem.cc b/kernel/mem.cc
index 593a97674..7520bc3db 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -784,12 +784,14 @@ namespace {
 			mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width);
 			mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
 			mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
+#ifndef ENABLE_VERIFIC_SYSTEMVERILOG
 			if (!is_compat) {
 				Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
 				for (int j = 0; j < n_wr_ports; j++)
 					if (wr_wide_continuation[j] != State::S1)
 						mwr.priority_mask.push_back(priority_mask[j] == State::S1);
 			}
+#endif
 			res.wr_ports.push_back(mwr);
 		}
 		if (is_compat) {