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Rename muxAB to postAddMux

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This commit is contained in:
Eddie Hung 2019-09-03 16:24:59 -07:00
parent cd002ad3fb
commit 16316aa05d
2 changed files with 25 additions and 44 deletions
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22
passes/pmgen/xilinx_dsp.cc
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@ -35,15 +35,15 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
#if 1 #if 1
log("\n"); log("\n");
log("ffA: %s\n", log_id(st.ffA, "--")); log("ffA: %s\n", log_id(st.ffA, "--"));
log("ffB: %s\n", log_id(st.ffB, "--")); log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--")); log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffM: %s\n", log_id(st.ffM, "--")); log("ffM: %s\n", log_id(st.ffM, "--"));
log("postAdd: %s\n", log_id(st.postAdd, "--")); log("postAdd: %s\n", log_id(st.postAdd, "--"));
log("muxAB: %s\n", log_id(st.muxAB, "--")); log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
log("ffP: %s\n", log_id(st.ffP, "--")); log("ffP: %s\n", log_id(st.ffP, "--"));
//log("muxP: %s\n", log_id(st.muxP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--"));
log("sigPused: %s\n", log_signal(st.sigPused)); log("sigPused: %s\n", log_signal(st.sigPused));
#endif #endif
log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp)); log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
@ -59,9 +59,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
SigSpec &opmode = cell->connections_.at("\\OPMODE"); SigSpec &opmode = cell->connections_.at("\\OPMODE");
if (st.ffP && st.muxAB) { if (st.ffP && st.postAddMux) {
opmode[4] = st.muxAB->getPort("\\S"); opmode[4] = st.postAddMux->getPort("\\S");
pm.autoremove(st.muxAB); pm.autoremove(st.postAddMux);
} }
else if (st.ffP && C == P) { else if (st.ffP && C == P) {
C = SigSpec(); C = SigSpec();

47
passes/pmgen/xilinx_dsp.pmg
View file

@ -3,8 +3,8 @@ pattern xilinx_dsp
state <SigBit> clock state <SigBit> clock
state <std::set<SigBit>> sigAset sigBset state <std::set<SigBit>> sigAset sigBset
state <SigSpec> sigC sigM sigMused sigP sigPused state <SigSpec> sigC sigM sigMused sigP sigPused
state <Cell*> postAdd muxAB state <Cell*> postAdd postAddMux
state <IdString> postAddAB state <IdString> postAddAB postAddMuxAB
match dsp match dsp
select dsp->type.in(\DSP48E1) select dsp->type.in(\DSP48E1)
@ -105,10 +105,9 @@ match postAdd
// Ensure that Z mux is not already used // Ensure that Z mux is not already used
if port(dsp, \OPMODE).extract(4,3).is_fully_zero() if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
select postAdd->type.in($postAdd) select postAdd->type.in($add)
select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool() select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool()
choice <IdString> AB {\A, \B} choice <IdString> AB {\A, \B}
define <IdString> AB_WIDTH (AB == \A ? \A_WIDTH : \B_WIDTH)
select nusers(port(postAdd, AB)) == 2 select nusers(port(postAdd, AB)) == 2
filter GetSize(port(postAdd, AB)) <= GetSize(sigP) filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB))) filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
@ -172,39 +171,21 @@ code ffP sigP clock
} }
endcode endcode
match muxA match postAddMux
if postAdd if postAdd
select muxA->type.in($mux) if ffP
select nusers(port(muxA, \Y)) == 2 select postAddMux->type.in($mux)
index <SigSpec> port(muxA, \A) === sigP select nusers(port(postAddMux, \Y)) == 2
index <SigSpec> port(muxA, \Y) === sigC choice <IdString> AB {\A, \B}
index <SigSpec> port(postAddMux, AB) === sigP
index <SigSpec> port(postAddMux, \Y) === sigC
set postAddMuxAB AB
optional optional
endmatch endmatch
match muxB code sigC
if postAdd if (postAddMux)
select muxB->type.in($mux) sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
select nusers(port(muxB, \Y)) == 2
index <SigSpec> port(muxB, \B) === sigP
index <SigSpec> port(muxB, \Y) === sigC
optional
endmatch
code sigC muxAB
if (muxA) {
muxAB = muxA;
sigC = port(muxAB, \B);
}
if (muxB) {
muxAB = muxB;
sigC = port(muxAB, \A);
}
if (muxAB) {
// Ensure that postAdder is not used
SigSpec opmodeZ = port(dsp, \OPMODE).extract(4,3);
if (!opmodeZ.is_fully_zero())
reject;
}
endcode endcode
code code