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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)

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This commit is contained in:
Clifford Wolf 2013-03-31 11:19:11 +02:00
parent 5640b7d607
commit 161565be10
5 changed files with 15 additions and 3 deletions
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2
frontends/verilog/parser.y
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@ -607,7 +607,7 @@ always_stmt:
ast_stack.pop_back();
} |
attr TOK_INITIAL {
AstNode *node = new AstNode(AST_ALWAYS);
AstNode *node = new AstNode(AST_INITIAL);
append_attr(node, $1);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);