mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-21 05:13:40 +00:00
Code Activity

Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)

Browse source
This commit is contained in:
Clifford Wolf 2013-03-31 11:19:11 +02:00
parent 5640b7d607
commit 161565be10
5 changed files with 15 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/ast/simplify.cc
View file

@ -196,7 +196,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
current_block = this;
current_block_child = children[i];
}
if (type == AST_ALWAYS && children[i]->type == AST_BLOCK)
if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK)
current_top_block = children[i];
did_something_here = children[i]->simplify(const_fold_here, at_zero, in_lvalue_here, stage);
if (did_something_here)