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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)

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This commit is contained in:
Clifford Wolf 2013-03-31 11:19:11 +02:00
parent 5640b7d607
commit 161565be10
5 changed files with 15 additions and 3 deletions
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4
frontends/ast/genrtlil.cc
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@ -310,6 +310,7 @@ struct AST_INTERNAL::ProcessGenerator
case AST_COND:
case AST_ALWAYS:
case AST_INITIAL:
for (auto child : ast->children)
if (child->type == AST_BLOCK)
collect_lvalues(reg, child, type_eq, type_le, false);
@ -1013,7 +1014,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
break;
// use ProcessGenerator for always blocks
case AST_ALWAYS: {
case AST_ALWAYS:
case AST_INITIAL: {
AstNode *always = this->clone();
ProcessGenerator generator(always);
delete always;