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verilog_parser: fix locations of warnings for restrict keyword

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This commit is contained in:
Emil J. Tywoniak 2025-08-13 10:56:48 +02:00
parent 910ff3ff36
commit 1603828b30
1 changed files with 2 additions and 2 deletions
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4
frontends/verilog/verilog_parser.y
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@ -2585,7 +2585,7 @@ assert:
node->str = *$1;
}
if (!$3)
warn_at_loc(@$, "SystemVerilog does not allow \"restrict\" without \"property\".");
warn_at_loc(@3, "SystemVerilog does not allow \"restrict\" without \"property\".");
} |
opt_sva_label TOK_RESTRICT opt_property TOK_LPAREN TOK_EVENTUALLY expr TOK_RPAREN TOK_SEMICOL {
if (mode->norestrict) {
@ -2596,7 +2596,7 @@ assert:
node->str = *$1;
}
if (!$3)
warn_at_loc(@$, "SystemVerilog does not allow \"restrict\" without \"property\".");
warn_at_loc(@3, "SystemVerilog does not allow \"restrict\" without \"property\".");
};
assert_property: