From 1603828b30c997ffe1cd237fad292e5de27c8c6a Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 13 Aug 2025 10:56:48 +0200
Subject: [PATCH] verilog_parser: fix locations of warnings for restrict
 keyword

---
 frontends/verilog/verilog_parser.y | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e8ca5d078..e299d3148 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2585,7 +2585,7 @@ assert:
 				node->str = *$1;
 		}
 		if (!$3)
-			warn_at_loc(@$, "SystemVerilog does not allow \"restrict\" without \"property\".");
+			warn_at_loc(@3, "SystemVerilog does not allow \"restrict\" without \"property\".");
 	} |
 	opt_sva_label TOK_RESTRICT opt_property TOK_LPAREN TOK_EVENTUALLY expr TOK_RPAREN TOK_SEMICOL {
 		if (mode->norestrict) {
@@ -2596,7 +2596,7 @@ assert:
 				node->str = *$1;
 		}
 		if (!$3)
-			warn_at_loc(@$, "SystemVerilog does not allow \"restrict\" without \"property\".");
+			warn_at_loc(@3, "SystemVerilog does not allow \"restrict\" without \"property\".");
 	};
 
 assert_property: