mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity

$__ABC_REG to have WIDTH parameter

Browse source
This commit is contained in:
Eddie Hung 2019-09-19 19:37:45 -07:00
parent e09f80479e
commit 1602516a8b
2 changed files with 18 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

3
techlibs/xilinx/abc_unmap.v
View file

@ -27,7 +27,8 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
assign Y = A;
endmodule
module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q);
module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
parameter WIDTH = 1;
assign O = I;
endmodule
(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)