mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-02 12:37:53 +00:00
Code Activity

Fix "make vgtest" so it runs to the end (but now it fails ;)

Browse source 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-09-22 17:34:20 +02:00
parent 3931b3a03f
commit 15fb0107dc
40 changed files with 79 additions and 79 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/simple/defvalue.sv
View file

@ -1,4 +1,4 @@
module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
module defvalue_top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
cnt #(1) foo (.clock, .cnt(cnt1), .delta);
cnt #(2) bar (.clock, .cnt(cnt2));
endmodule