mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 20:21:25 +00:00
Code Activity

Fix "make vgtest" so it runs to the end (but now it fails ;)

Browse source 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-09-22 17:34:20 +02:00
parent 3931b3a03f
commit 15fb0107dc
40 changed files with 79 additions and 79 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/simple/attrib08_mod_inst.v
View file

@ -1,4 +1,4 @@
module bar(clk, rst, inp, out);
module attrib08_bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
@ -10,13 +10,13 @@ module bar(clk, rst, inp, out);
endmodule
module foo(clk, rst, inp, out);
module attrib08_foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
(* my_module_instance = 99 *)
bar bar_instance (clk, rst, inp, out);
attrib08_bar bar_instance (clk, rst, inp, out);
endmodule