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Fix "make vgtest" so it runs to the end (but now it fails ;)
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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40 changed files with 79 additions and 79 deletions
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@ -1,4 +1,4 @@
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function [7:0] do_add;
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function [7:0] attrib07_do_add;
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input [7:0] inp_a;
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input [7:0] inp_b;
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@ -6,7 +6,7 @@ function [7:0] do_add;
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endfunction
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module foo(clk, rst, inp_a, inp_b, out);
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module attri07_foo(clk, rst, inp_a, inp_b, out);
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input wire clk;
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input wire rst;
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input wire [7:0] inp_a;
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@ -15,7 +15,7 @@ module foo(clk, rst, inp_a, inp_b, out);
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always @(posedge clk)
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if (rst) out <= 0;
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else out <= do_add (* combinational_adder *) (inp_a, inp_b);
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else out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b);
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endmodule
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