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Fix "make vgtest" so it runs to the end (but now it fails ;)

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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-09-22 17:34:20 +02:00
parent 3931b3a03f
commit 15fb0107dc
40 changed files with 79 additions and 79 deletions
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6
tests/simple/attrib02_port_decl.v
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@ -1,4 +1,4 @@
module bar(clk, rst, inp, out);
module attrib02_bar(clk, rst, inp, out);
(* this_is_clock = 1 *)
input wire clk;
(* this_is_reset = 1 *)
@ -13,13 +13,13 @@ module bar(clk, rst, inp, out);
endmodule
module foo(clk, rst, inp, out);
module attrib02_foo(clk, rst, inp, out);
(* this_is_the_master_clock *)
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
attrib02_bar bar_instance (clk, rst, inp, out);
endmodule