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Separate out CREG packing into new pattern, to avoid conflict with PREG
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parent
26a6c55665
commit
15dfbc8125
4 changed files with 273 additions and 46 deletions
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@ -4,11 +4,11 @@ udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffDrstpol ffMrstpol ffPrstpol
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state <Cell*> ffAD ffADcemux ffADrstmux ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux ffC ffCcemux ffCrstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux
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state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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@ -24,7 +24,7 @@ match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code sigA sigB sigC sigD sigM
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code sigA sigB sigC sigD sigM clock
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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@ -54,6 +54,8 @@ code sigA sigB sigC sigD sigM
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}
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else
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sigM = P;
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clock = port(dsp, \CLK, SigBit());
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endcode
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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@ -326,26 +328,6 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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if (param(dsp, \CREG).as_int() == 0 && sigC != sigP) {
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffCrstmux = dffrstmux;
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ffCrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffCcemux = dffcemux;
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ffCcepol = dffcepol;
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}
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sigC = dffD;
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}
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}
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endcode
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match overflow
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if ffP
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if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET"
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