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verilog: support for time scale delay values

This commit is contained in:
Zachary Snow 2022-02-11 22:57:31 +01:00 committed by Zachary Snow
parent 68c67c40ec
commit 15a4e900b2
4 changed files with 42 additions and 4 deletions

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@ -0,0 +1,25 @@
logger -expect-no-warnings
read_verilog -sv <<EOT
module top;
wand x;
`define TEST(time_scale) if (1) assign #time_scale x = 1;
`TEST(1s)
`TEST(1ms)
`TEST(1us)
`TEST(1ns)
`TEST(1ps)
`TEST(1fs)
`TEST((1s))
`TEST(( 1s))
`TEST((1s ))
`TEST(( 1s ))
`TEST(1.0s)
`TEST(1.1s)
`TEST(1.0e-1s)
`TEST(1e-1s)
endmodule
EOT