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Adding check for BLIF names command input plane size.
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parent
db73f3c26b
commit
15a0697c70
2 changed files with 17 additions and 1 deletions
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@ -21,6 +21,8 @@
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YOSYS_NAMESPACE_BEGIN
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const int lut_input_plane_limit = 12;
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static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f)
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{
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string strbuf;
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@ -513,6 +515,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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sopmode = -1;
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lastcell = sopcell;
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}
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else if (input_sig.size() > lut_input_plane_limit)
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{
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err_reason = stringf("names' input plane must have fewer than 13 signals.");
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goto error_with_reason;
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}
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else
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{
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RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
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@ -576,7 +583,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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if (lutptr)
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{
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if (input_len > 12)
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if (input_len > lut_input_plane_limit)
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goto error;
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for (int i = 0; i < (1 << input_len); i++) {
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