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Replacing new usages of selected_*

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This commit is contained in:
Krystine Sherwin 2024-11-25 17:46:11 +13:00
parent 89c5ff0a39
commit 15852de703
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2 changed files with 22 additions and 22 deletions
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8
kernel/rtlil.cc
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@ -1287,7 +1287,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
std::vector<RTLIL::Module*> result;
result.reserve(modules_.size());
for (auto &it : modules_)
if (selected_whole_module(it.first) || (include_partials && selected_module(it.first))) {
if (is_selected_whole_module(it.first) || (include_partials && is_selected_module(it.first))) {
if (!(exclude_boxes && it.second->get_blackbox_attribute(ignore_wb)))
result.push_back(it.second);
else
@ -1314,7 +1314,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
default:
break;
}
} else if (!include_partials && selected_module(it.first)) {
} else if (!include_partials && is_selected_module(it.first)) {
switch(partials)
{
case RTLIL::SELECT_WHOLE_WARN:
@ -2541,12 +2541,12 @@ bool RTLIL::Module::has_processes_warn() const
bool RTLIL::Module::is_selected() const
{
return design->selected_module(this->name);
return design->is_selected_module(this->name);
}
bool RTLIL::Module::is_selected_whole() const
{
return design->selected_whole_module(this->name);
return design->is_selected_whole_module(this->name);
}
std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const