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Add new tests for ice40 architecture

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SergeyDegtyar 2019-08-20 07:50:05 +03:00
parent 749ff864aa
commit 153ec0541c
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tests/ice40/add_sub.ys Normal file
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equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
synth_ice40
select -assert-count 12 t:SB_LUT4
select -assert-count 7 t:SB_CARRY
select -assert-count 2 t:$logic_and
select -assert-count 2 t:$logic_or
write_verilog ./temp/add_sub_synth.v