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Add Xilinx dist RAM as comb boxes

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This commit is contained in:
Eddie Hung 2019-06-24 21:54:01 -07:00
parent 49a762ba46
commit 152e682bd5
2 changed files with 16 additions and 0 deletions
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2
techlibs/xilinx/cells_sim.v
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@ -281,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc_box_id = 4, abc_scc_break="D" *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -298,6 +299,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 5, abc_scc_break="D" *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,